Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-24
2004-06-15
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S318000, C365S185040
Reexamination Certificate
active
06750504
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a memory cell and array, and more particularly, to a flash memory cell and array.
2. Description of the Prior Art
In non-volatile memories, flash memory cells can be programmed by various types of operating methods such as channel hot electron injection and Fowler-Nordheim (FN) tunneling. During a programming operation of the flash memory cell, electrons are driven into a floating gate to increase a critical voltage of the flash memory cell. During an erasing operation of the memory cell, electrons are drawn from the floating gate to decrease the critical voltage of the flash memory cell.
In order to program and erase a staked gate flash memory cell, carriers pass through an insulator potential barrier built from the floating gate and terminals of other devices. Therefore, the electrons are conducted within an oxide layer in the stacked gate flash memory cell. Please refer to FIG.
1
.
FIG. 1
is a schematic diagram illustrating a hot electron injection mode of a conventional flash memory cell
10
. A proper positive voltage is applied to a control gate
12
and a drain
14
of the flash memory cell
10
to open the flash memory cell
10
. At this time, the flash memory cell
10
is in a high drain voltage state, and carriers in a channel of the flash memory cell
10
eject from a source
16
to the drain
14
and the carriers are sped up at the drain
14
by a high channel electric field. As long as the carriers enter into a high electric field region, the carriers will be sped up to form a series of collisions. After the collision between the carriers and silicon lattices, electron-hole pairs are generated, and then the electron-hole pairs collide again by speeding up from the electric field. Therefore, a part of the carriers with high kinetic energy eject through the silicon oxide layer
18
and into the floating gate
20
so as to store the carriers in the floating gate
20
.
However, the flash memory cell
10
has to be opened when the flash memory cell
10
is programmed in the hot electron injection mode for storing information. Therefore, a channel current in the channel of the flash memory cell
10
is generated so as to dissipate power of the flash memory cell
10
.
In order to solve the above-mentioned power consumption problem, the flash memory cell can be programmed by using the FN tunneling mode. Please refer to FIG.
2
.
FIG. 2
is a cross-sectional diagram illustrating the FN tunneling mode of a conventional flash memory cell
30
. The flash memory cell
30
comprises a deep P-well
26
utilized as a substrate of the flash memory cell
30
, an N-well
28
formed on the deep P-well
26
, a gate structure including a control gate
34
, a floating gate
36
, and a silicon oxide layer
38
from top to bottom, and a source
41
and a drain
32
formed in the N-well
28
. The flash memory cell
30
further comprises a P-type ion doped region
42
formed in the N-well
28
and under and surrounding the source
41
and at least a portion of a bottom of the gate oxide layer
38
, a metal contact V
S
penetrating through the source
41
and electrically connected to the source
41
and the P-type ion doped region
42
, and another metal contact V
D
electrically connected to the drain
32
. In addition, the metal contact V
S
can only be electrically connected to the source
41
and the P-type ion doped region
42
, and does not penetrate through the source
41
. When the flash memory cell
30
is programmed, electrons
40
in a channel of the flash memory cell
30
are ejected into the floating gate
36
through the gate oxide layer
38
.
A flash memory array composed of a plurality of the above flash memory cells
30
shown in
FIG. 2
is shown in FIG.
3
A and FIG.
3
B.
FIG. 3A
is a cross-sectional diagram illustrating a bit line connection mode of a conventional flash memory cell.
FIG. 3B
is a corresponding circuit diagram of the flash memory cell shown in FIG.
3
A. Please refer to FIG.
3
A. All of the flash memory cells
30
are built in an N-well
11
. When a selected flash memory cells
30
is programmed, a power supplied from a bit line
13
affects the other flash memory cells
30
which connected to the same bit line
30
. For example, when 5 Volts is applied to the bit line
13
, drains (which are connected to the N-well
11
) of the other flash memory cells
30
have a voltage of slightly less than 5 Volts. This forms M−1 interferences in a selected sector and M*P/E cycle times*(N−1) in the other sectors if the flash memory has N sectors, and each of the sectors has M word lines. That is, M is equal to the number of the flash memory cells. The cycle times means average interferences in each sector when the flash memory cell is programmed. Therefore, the total programming interferences of the bit line are M*P/E cycle times* (N−1)+(M−1) during the period when the flash memory cells
30
are programmed.
Similarly, erasing interferences of the bit line occur when the flash memory cells
30
are erased. However, the flash memory cells
30
of a whole sector are erased once, not one by one. When 8 Volts is applied to a drain
32
of the flash memory cell
30
,the whole N-well
11
has a voltage of about 8 Volts. Therefore, the erasing interferences of the other sectors are P/E cycle times*(N−1).
The above-mentioned programming and erasing interferences influence the information storage capability of the flash memory cell, and cause information to be lost very easily. In addition, connection between a source and a P-type ion doped region (i.e. a shallow P-well)
15
of each flash memory cell
30
by the bit line
13
forms a parasitic capacitance
17
at the source of the flash memory cell
30
, as shown in FIG.
3
B. Therefore, the parasitic capacitance
17
burdens the bit line
13
and thus lowers the reading speed when the flash memory cell
30
is read.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a low voltage single-poly flash memory cell and array to solve the problems of high power consumption and high operating voltage of the conventional flash memory cell. Moreover, the claimed invention utilizes only one polysilicon layer, which is different from the stacked gate of the conventional flash memory cell, so as to simplify the fabrication process.
It is another object of the claimed invention to provide a flash memory cell having a divided bit line to prevent the above overloading of the bit line from being generated.
It is another object of the claimed invention to provide another flash memory cell having a divided bit line to reduce interferences efficiently when the flash memory cell is programmed or erased.
According to the claimed invention, a low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer including a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well, a gate located on the charge storage layer, a source of the second conductivity type located in the second ion well and being in contact with the charge storage layer, an ion doped region of the first conductivity type formed in the second ion well and under and surrounding the source and at least a portion of a bottom of the first insulating layer, and a drain of the second conductivity type located in the second ion well and being in contact with the ion doped region and the charge layer.
According to the claimed invention, another low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a third ion well of the first conductivity type formed on the second ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the third ion well, a gate loc
Hsu Ching-Hsiang
Shen Shih-Jye
Wong Wei-Zhe
Yang Ching-Sung
e-Memory Technology, Inc.
Hsu Winston
Wojciechowicz Edward
LandOfFree
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