Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-06-16
2000-10-03
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
061287571
ABSTRACT:
A method for improving the fault coverage of functional tests for integrated circuits by establishing a design-specific low voltage functional screening procedure. In the disclosed embodiment of the invention, a reduced voltage test threshold is established by comparing the results of an iterative test procedure executed on a set of known good integrated circuits and integrated circuits which have passed traditional functional test programs but manifested problems in the field. For a given device under test, the iterative procedure commences by applying a system clock and nominal power supply voltage. A set of functional test vectors is then executed on the device using automated test equipment (ATE). The results are compared with expected test results to determine if the device is a passing device under the initial test conditions. If so, the power supply voltage is decremented by a predetermined value and the test process is repeated. This iterative process continues until the device under test fails the functional test. At this point, the power supply voltage at which the device under test has failed functional testing or, alternatively, the previous power supply voltage, is stored in a database. The testing procedure is then repeated for a statistically significant group of additional known good parts/bad parts. After databases have been compiled for the good and bad parts, the results of the testing procedure are examined to determine the voltage below which substantially all the known good parts pass and above which substantially all the bad parts fail. This voltage is then utilized as the reduced voltage test threshold value for a production test program. Additional information relating to the integrity of the semiconductor process used to manufacture the devices under test may also be compiled to verify that the results of the test development procedure have not been skewed.
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Nguyen Hai Xuan
Stewart Veronica Collaco
Yousuf Syed Hasan
LSI Logic Corporation
Nguyen Hoa T.
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