Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-02-29
2003-08-12
Lee, Michael G. (Department: 2876)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000, C326S040000, C326S101000, C257S315000
Reexamination Certificate
active
06605961
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits and, more particularly, to structures and methods for low voltage PLA's with ultra thin tunnel oxides.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read only memories (EEPROMs) provide nonvolatile data storage. EEPROM memory cells typically use field-effect transistors (FETs) having an electrically isolated (floating) gate that affects conduction between source and drain regions of the FET. A gate dielectric is interposed between the floating gate and an underlying channel region between source and drain regions. A control gate is provided adjacent to the floating gate, separated therefrom by an intergate dielectric.
In such memory cells, data is represented by charge stored on the polysilicon floating gates. The charge is placed on the floating gate during a write operation using a technique such as hot electron injection or Fowler-Nordheim (FN) tunneling. Fowler-Nordheim tunneling is typically used to remove charge from the polysilicon floating gate during an erase operation. At the present time, FN tunneling is primarily used (see generally, T. P. Ma et al., “Tunneling leakage current in ultrathin (<4 nm) nitride/oxide stack dielectrics,” IEEE Electron Device Letters, vol. 19, no. 10, pp. 388-390, 1998) as shown in
FIG. 1A
where the electrons are injected into the conduction band of the oxide by driving the floating gate with a negative potential. Another type of tunneling which has been used is band to band, BTB, tunneling (see generally C. Salm et al., “Gate current and oxide reliability in P+poly MOS capacitors with poly-Si and Poly-Ge
0.3
Si
0.7
gate material,” IEEE Electron Device Letters, vol. 19, no. 7, pp. 213-215, July 1998) as shown in
FIG. 1B
where electrons tunnel out of the valence band, in this case of the silicon substrate, on to the floating gate which is driven to a positive potential.
A flash EEPROM cell has the potential to be smaller and simpler than today's conventional dynamic random access memory (DRAM) cell. One of the limitations to shrinking a flash EEPROM memory cell has been the requirement for a silicon dioxide gate insulator thickness of approximately 10 nm between the floating polysilicon gate and the silicon substrate forming the channel of a flash field effect transistor. This gate thickness is required to prevent excess charge leakage from the floating gate that would reduce data retention time (targeted at approximately 10 years)
Current n-channel flash memories utilize a floating polysilicon gate over a silicon dioxide gate insulator of thickness of the order 100 Å or 10 nm in a field effect transistor. (See generally, B. Dipert et al.,
IEEE Spectrum
, pp. 48-52 (Oct. 1993). This results in a very high barrier energy of around 3.2 eV for electrons between the silicon substrate and gate insulator and between the floating polysilicon gate and silicon oxide gate insulator. This combination of barrier height and oxide thickness results in extremely long retention times even at 250 degrees Celsius. (See generally, C. Papadas et al.,
IEEE Trans. on Electron Devices
, 42, 678-681 (1995)). The simple idea would be that retention times are determined by thermal emission over a 3.2 electron volt (eV) energy barrier, however, these would be extremely long so the current model is that retention is limited by F-N tunneling off of the charged gate. This produces a lower “apparent” activation energy of 1.5 eV which is more likely to be observed. Since the retention time is determined either by thermal excitation of electrons over the barrier or the thermally assisted F-N tunneling of electrons through the oxide, retention times are even longer at room temperature and/or operating temperatures and these memories are for all intensive purposes non-volatile and are also known as non volatile random access memories (NVRAMs). This combination of barrier height and tunnel oxide thickness is not an optimum value in terms of transfer of electrons back and forth between the substrate and floating gate and results in long erase times in flash memories, typically of the order of milliseconds. To compensate for this, a parallel erase operation is performed on a large number of memory cells to effectively reduce the erase time, whence the name “flash” or “flash EEPROM” originated since this effective erase time is much shorter than the erase time in EEPROMs.
P-channel flash memory cells, having gate oxide thicknesses of approximately 100 Å, have been reported (see generally, T. Ohnakado et al.,
Digest of Int. Electron Devices Meeting
, Dec. 10-13, 1995, Washington D.C., pp. 279-282; T. Ohnakado et al.,
Digest of Int. Electron Devices Meeting
, Dec. 8-11, 1996, San Francisco, pp. 181-184; T. Ohnakado et al.,
Proc. Symposium on VLSI Technology
, Jun. 9-11, 1998), Honolulu, Hi., pp. 14-15) and disclosed (see U.S. Pat. No. 5,790,455, issued Aug. 4, 1998, entitled “Low voltage single supply CMOS electrically erasable read-only memory”). These reported and disclosed p-channel flash memory cells work similar to n-channel flash memory cells in that they utilize hot electron effects to write data on to the floating gate. If the magnitude of the drain voltage in a PMOS transistor is higher than the gate voltage, then the electric field near the drain through the gate oxide will be from the gate (most positive) towards the drain (most negative). This can and will cause hot electrons to be injected into the oxide and collected by the floating gate. The mechanisms reported are either channel hot electron injection, CHE, or band-to-band tunneling induced hot electron injection, BTB. The gate current in PMOS transistors (see generally, I. C. Chen et al.,
IEEE Electron Device Lett
., 4:5, 228-230 (1993); and J. Chen et al.,
Proceedings TREE Int. SOT Conf
., Oct. 1-3, 1991, pp. 8-9) can actually be much higher than the gate current in NMOS transistors (see generally, R. Ghodsi et al.,
IEEE Electron Device Letters
, 19:9, 354-356 (1998)) due to the BTB tunneling. Negatively, higher gate current in the PMOS transistors resulting from this BTB tunneling effect limits the reliability of deep sub-micron CMOS technology, as reported by R. Ghodsi et al. In other words, the reliability of the PMOS array is lowered because of this higher current in the PMOS device.
In co-pending, commonly assigned U.S. patent applications: entitled “Dynamic Flash Memory Cells with UltraThin Tunnel Oxides,” attorney docket no. 303.682US1, Ser. No. 09/513,938, and “P-Channel Dynamic Flash Memory Cells with UltraThin Tunnel Oxides,” attorney docket no. 303.684US1, Ser. No. 09/514,627, dynamic memory cells base on floating gates, like those in flash memory cells, over ultrathin tunneling oxides, are disclosed. In these cases write and erase was accomplished by tunneling through the ultrathin gate oxides. The dynamic nature of the cell resulted from using relatively speaking larger potential variations and amounts of charge stored on the floating gates, as a consequence charge could leak on to, or off of, the floating gate by tunneling of carriers to allowed states in the conduction bands of the insulator, FN tunneling, or semiconductor by band to band, BTB, tunneling. The transistors employed there were normal enhancement mode n-channel MOSFETs, or enhancement mode PMOSFETs. However, the dynamic nature of the cells disclosed therein are not suited for the non volatile requirements of programmable logic arrays.
As described above, tunneling has long been used in the erase operation of flash memory devices. Such flash memory devices have further been used in field programmable logic devices such as circuit programmable logic devices, programmable memory address decode and fault-tolerant memory arrays, and embedded functions. However, the use of conventional flash memory devices in such circuit applications suffer the above described drawbacks relating to the speed of the write and erase functions.
Thus, there remains a need in the art to develop “stat
Lee Michael G.
Micro)n Technology, Inc.
Paik Steven S.
Schwegman Lundberg Woessner & Kluth P.A.
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