Low voltage NMOS-based electrostatic discharge clamp

Details Low voltage NMOS-based electrostatic discharge clamp Low voltage NMOS-based electrostatic discharge clamp

2005-01-18

2005-01-18

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S358000, C257S360000

Reexamination Certificate

active

06844597

ABSTRACT:
Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

REFERENCES:
patent: 5686751 (1997-11-01), Wu
patent: 6291862 (2001-09-01), Chevallier
patent: 6329692 (2001-12-01), Smith
Joshi et al., “ESD protection form BiCMOS circuits,”IEEE BCTM Proceedings, 12.5: 218-221, 2000.

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