Low voltage junction and high voltage junction optimization for

Details Low voltage junction and high voltage junction optimization for Low voltage junction and high voltage junction optimization for

1998-07-02

2000-12-12

Elms, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438976, 438275, 438258, 438266, H01L 21336, H01L 218234

Patent

active

061597953

ABSTRACT:
An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.

REFERENCES:
patent: 4775642 (1988-10-01), Chang et al.
patent: 5194924 (1993-03-01), Komori et al.
patent: 5395778 (1995-03-01), Walker
patent: 5449634 (1995-09-01), Inoue
patent: 5516713 (1996-05-01), Hsue et al.
patent: 5574685 (1996-11-01), Hsu
patent: 5668034 (1997-09-01), Sery et al.
patent: 5679585 (1997-10-01), Gardner et al.
patent: 5783471 (1998-07-01), Chu
patent: 5879990 (1999-03-01), Dormans et al.
patent: 5942780 (1999-08-01), Barsan et al.

Affiliated with

Also associated with

Rating

Low voltage junction and high voltage junction optimization for does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low voltage junction and high voltage junction optimization for , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low voltage junction and high voltage junction optimization for will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-216152