Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-12-06
1998-07-14
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438266, 438270, H01L 218247
Patent
active
057803412
ABSTRACT:
A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate is provided. A substrate is provided having source and drain region with a channel therebetween. A floating gate structure is formed over portions of the source and drain regions and the channel. The structure includes a dielectric layer and a conductor layer thereover. The channel under the floating gate has both horizontal and vertical components. After forming the vertical and horizontal components, an N- drain region is formed in self-alignment with the vertical channel step region's edge. The depth of the N- drain is greater than the source region.
REFERENCES:
patent: 4531203 (1985-07-01), Masuoka et al.
patent: 4561004 (1985-12-01), Kuo et al.
patent: 5198380 (1993-03-01), Harari
patent: 5376572 (1994-12-01), Yang et al.
patent: 5591652 (1997-01-01), Matsushita
A. Phillips et al, 1975 IEDM Technical Digest, p. 39 "N Channel IGFET Design Limitations due to TBT Electron Trapping".
T. Ning et al, "Emission Probability of Hotelectron from Silicon into Silicon Dioxide", J. Applied Physics, 1977, vol. 48, pp. 286-293.
"A Fully Decoded 2048 Bit Electrically-Programmable MOS-ROM", 1971 ISSCC, pp. 80-81.
"FAMOS-A New Semiconductor Charge Storage Device" Solid State Electronics, 1974, vol. 17, pp. 517-529.
"Operation and Characterization of N-Channel EPROM Cell" J. Barnes et al in 1976 IEDM, pp. 177-179.
P. Salsburg, "High Performance MOS EPROM Using a Stack Gate Cell", in 1977 ISSCC, pp. 186-187.
Cheming Hu, "Lucky-electron Model of Channel Hot Electron Emission", IEDM, 1970, pp. 223-226.
G. Samachusa et al. "128K Flash EEPROM Using Double Polysilicon Technology", 1987 Journal of Solid State Circuits, vol. SC-22, No. 5, pp. 676-682.
H. Kume, "Flash-Erase EEPROM Cell with an Asymmetric Source and Data Structure", Technical Digest of the IEEE International Elec Dev Mtg, Dec. 1977 pp. 560-563.
V.N. Kynett et al, "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory", IEEE J. Solid State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1157-1162.
J. Kupec et al, "Triple Level Polysilicon EEPROM with Single Transistor Per Bit", 1980 IEDM Technical Digest, pp. 602-606.
Wu et al, "A Novel High-Speed 5-v Programming EPROM Structure with Source-Side Injection" 1986 IEDM Technical Digest, pp. 584-587.
Ackerman Stephen B.
Chaudhari Chandra
Halo LSI Design & Device Technology, Inc.
Saile George O.
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