Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-12-09
1998-07-28
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438305, 438307, 438595, 438981, H01L 218238
Patent
active
057862478
ABSTRACT:
The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is operable over a range of voltages (e.g., a range from below 3 volts to a range over 5 volts) without producing unbalanced operation of n-channel and p-channel transistors. Thus, integrated circuits formed in accordance with the present invention can be operated at different voltage power sources without requiring a redesign or relayout of the integrated circuit. In accordance with the present invention, CMOS transistors can be fabricated without increased fabrication complexity to provide transistors which operate within a relatively safe region of their operating characteristics and which operate with a speed that is unaffected by the reduced voltage supply (i.e., no need to accommodate timing errors since both n-channel and p-channel transistor performance remains balanced).
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"Applications of Anisotroptic Plasma Etching" Muraka: Electronic Materials Science and Technology, pp. 524-527.
Chang Kuang-Yeh
Rao Ramachandr A.
Niebling John
Pham Long
VLSI Technology Inc.
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