Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-10-26
2010-02-02
Nguyen, Dao H (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
07655994
ABSTRACT:
A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
REFERENCES:
patent: 5763922 (1998-06-01), Chau
patent: 2001/0032995 (2001-10-01), Maria et al.
patent: 2003/0042557 (2003-03-01), Shimamoto et al.
patent: 2003/0067021 (2003-04-01), Ikeda et al.
patent: 2004/0188762 (2004-09-01), Shimamoto et al.
patent: 2005/0045938 (2005-03-01), Mutou et al.
patent: 2005/0151184 (2005-07-01), Lee et al.
patent: 2005/0253181 (2005-11-01), Kimizuka et al.
patent: 2005/0280104 (2005-12-01), Li
patent: 2006/0223248 (2006-10-01), Venugopal et al.
patent: 10 2004 048 679 (2005-05-01), None
Hobbs, et al., “Factors Influencing the Threshold Voltages of Metal Oxide CMOS Devices”, Techology Solutions Group, Motorola, ECS2004.
Deweerd, et al., “Potential remedies for the VT/Vrb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey”, Elsevier, Microelectronics Reliability 45 (2005), pp. 786-789.
Hobbs, et al., “Fermi Level Pinning at the PolySi/Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers, 4-89114-035-6/03.
Hobbs, et al., “Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface-Part I”, IEEE Transactions of Electron Devices, vol. 51, No. 6, Jun. 2004, pp. 971-977.
Lee, et al., “Optimized poly-Si/HfSiO low power devices with ideal threshold voltage and mobility”, IBM Semiconductor Research and Development Center.
Miyamura, et al., “Origin of Flatband Voltage Shift in Poly-Si/Hf-based High-k Gate Dielectrics and Vfb Dependence on Gate Stack Structure”, System Devices Research Laboratories, NEC Corp.
Cartier, et al., Systematic study of pFET Vt with Hf-based gate stacks with poly-Si and FUSI gates, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 44-45.
Punchaipeth, P., et al. “Effect of Nitrogen on Electrical and Physical Properties of Polyatomic Layer Chemical Vapor Deposition Hfsichioy Gate Dielectrics”, Japanese Journal of Applied Sciences, Japany Society of Applied Physics, Tokyo, JP, vol. 43, No. 11B, Nov. 1, 2004, pp. 7815-7820.
Iwamoto, T., et al., “A Highly Manufacturable Low Power and High Speed HfSiO CMOS FET with Dual Poly-Si Gate Electrodes”, International Electron Devices Meeting, 2003, New York, NY.
Cartier Eduard A.
Copel Mathew W.
Frank Martin M.
Gousev Evgeni P.
Jamison Paul C.
International Business Machines - Corporation
Nguyen Dao H
Nguyen Tram H
Percello, Esq. Louis J.
Scully , Scott, Murphy & Presser, P.C.
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