Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-06-30
1999-11-16
Fahmy, Wael M.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438194, 438282, 438289, 257336, 257344, 257345, 257404, 257408, H01L 21336
Patent
active
059857056
ABSTRACT:
A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance. A channel region comprising the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface. A second well region is disposed in the semiconductor substrate below the channel region, the second well region being of the first conductivity type having a second average dopant concentration. A buried electrode region is disposed below the source and drain regions between the second well region and the channel region. The buried electrode region has a dopant of the first conductivity type at a concentration which is greater than both the first and second dopant concentrations of the channel region and the second well region, respectively. Finally, a gate is disposed over the channel region with the buried electrode creating a low gate threshold voltage with significantly reduced likelihood of punch through.
REFERENCES:
patent: 5021853 (1991-06-01), Mistry
patent: 5060037 (1991-10-01), Rountree
patent: 5262344 (1993-11-01), Mistry
patent: 5272371 (1993-12-01), Bishop et al.
patent: 5493251 (1996-02-01), Khambaty et al.
patent: 5521415 (1996-05-01), Kondo
patent: 5529940 (1996-06-01), Yamamoto et al.
patent: 5589701 (1996-12-01), Baldi
patent: 5593911 (1997-01-01), Lee et al.
patent: 5616943 (1997-04-01), Nguyen et al.
patent: 5622880 (1997-04-01), Burr et al.
patent: 5623156 (1997-04-01), Watt
patent: 5629544 (1997-05-01), Voldman et al.
patent: 5650340 (1997-07-01), Burr et al.
patent: 5661045 (1997-08-01), Manning et al.
patent: 5719422 (1998-02-01), Burr et al.
patent: 5719733 (1998-02-01), Wei
patent: 5744839 (1998-04-01), Ma et al.
patent: 5751042 (1998-05-01), Yu
Fahmy Wael M.
LSI Logic Corporation
Pham Long
LandOfFree
Low threshold voltage MOS transistor and method of manufacture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low threshold voltage MOS transistor and method of manufacture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low threshold voltage MOS transistor and method of manufacture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1323989