Low temperature process to form elevated drain and source of...

Details Low temperature process to form elevated drain and source of... Low temperature process to form elevated drain and source of...

2001-02-12

2002-04-30

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000

Reexamination Certificate

active

06380043

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a process for forming elevated drain and source contact structures using relatively low temperatures to preserve the gate dielectric having a high dielectric constant for the field effect transistor having scaled down dimensions of tens of nanometers.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
As the dimensions of the MOSFET
100
are further scaled down, the thickness of the gate dielectric
116
is also scaled down. However, with a thinner gate dielectric
116
, more charge carriers tunnel through the thin gate dielectric
116
to result in undesired leakage current at the gate of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. To minimize such undesired leakage current, a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
) (i.e., a high-K dielectric material) is used for the gate dielectric
116
, as known to one of ordinary skill in the art of integrated circuit fabrication. The gate dielectric
116
has a higher thickness when comprised of such a high-K dielectric material than when comprised of silicon dioxide (SiO
2
) for the same drive current of the MOSFET
100
to minimize undesired tunneling current through the gate dielectric
116
.
In addition, as the dimensions of the MOSFET
100
are further scaled down, the thickness of the drain and source silicides
110
and
114
is also scaled down as the depth of the drain and source contact junctions
108
and
112
is scaled down. However, thinner drain and source silicides
110
and
114
with the lower volume of silicide result in higher resistance at the drain and source of the MOSFET
100
.
Referring to
FIG. 2
, to increase the volume of silicide, an elevated drain structure
132
is formed to be coupled to the drain extension junction
104
, and an elevated source structure
134
is formed to be coupled to the source extension junction
106
, as known to one of ordinary skill in the art of integrated circuit fabrication. Referring to
FIG. 3
, a drain silicide
142
is formed within the elevated drain structure
132
, and a source silicide
144
is formed within the elevated source structure
134
. Because the elevated drain and source structures
132
and
134
have higher thickness and are not limited to the depth of the drain and source contact junctions
108
and
112
, thicker drain and source silicides
142
and
144
may be formed with the elevated drain and source structures
132
and
134
to minimize the resistance at the drain and source of the MOSFET
100
.
In the prior art, the elevated drain and source structures
132
and
134
are comprised of silicon deposited by an epitaxy deposition process using a relatively high temperature in the range of from about 1100° Celsius to about 1200° Celsius. In addition, referring to
FIG. 2
, a contact dopant is implanted into the elevated drain and source structures
132
and
134
and activated in a thermal anneal process using a relatively high temperature in the range of from about 800° Celsius to about 1000° Celsius.
However, to minimize charge carrier tunneling through the gate dielectric
116
, a high-K dielectric material having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
) is used for the gate dielectric
116
. When the semiconductor substrate
102
is comprised of silicon, such high-K dielectric material, such as metal oxide for example, may react with the silicon semiconductor substrate
102
at any temperature greater than about 750° Celsius to degrade the gate dielectric
116
.
Nevertheless, elevated drain and source structures are desired for increasing the volume of the drain and source silicides while a gate dielectric comprised of a high-K dielectric material is also desired for minimizing charge carrier tunneling through the gate dielectric, as the dimensions of the MOSFET are further scaled down. Thus, a mechanism is desired for fabricating drain and source silicides with elevated drain and source contact structures using temperatures below about 750° Celsius to preserve the integrity of the gate dielectric comprised of a high-K dielectric material.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, elevated drain and source contact structures are formed with deposition of an in-situ doped amorphous semiconductor material using a temperature of less than about 500° Celsius. In addition, an amorphization dopant is implanted into the drain and source extension junctions such that extension dopant within the drain and source extension junctions and contact dopant within the elevated drain and source contact structures are activated using a temperature of less than about 600° Celsius.
In one embodiment of the present invention, a field effect transistor is fabricated within an active device area of a semiconductor substrate. A gate structure is formed on a gate dielectric on the active device area of the semiconductor substrate, and the gate dielectric has a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
). An amorphization dopant and an extension dopant are implanted into exposed regions of the active device area of the semiconductor substrate.
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