Low temperature process for post-etch defluoridation of metals

Details Low temperature process for post-etch defluoridation of metals Low temperature process for post-etch defluoridation of metals

1997-12-11

2000-10-31

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438709, 438710, 438720, 438745, 438754, H01L 21311

Patent

active

061402435

ABSTRACT:
An integrated circuit fabrication process in which residual fluorine contamination on metal surfaces after ashing is removed by exposure to an NH.sub.3 /O.sub.2 plasma.

REFERENCES:
patent: 4430152 (1984-02-01), Okano
patent: 5700740 (1997-12-01), Chen et al.
Pearson, et al.; Low bias dry etching of tungsten and dielectric layers on GaAs; Semiconductor Science and Technology, vol. 8, No. 10, Oct. 1, 1993 pp. 1897-1903; XP000417423.

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