Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-14
2001-07-31
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S937000
Reexamination Certificate
active
06268274
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a structure and process for fabricating an inter metal dielectric layer for integrated circuits interconnecting active and passive elements. More particularly, this invention relates to a structure and process for an inter metal dielectric layer formed using electron cyclotron resonance techniques employing high density plasma (HDP) and chemical vapor deposition (CVD) processes. A unique HDP-CVD two step deposition process is described that allows cooling between the steps thereby providing metal circuitry possessing no warping or distortion.
2. Description of the Prior Art
Integrated circuitry (IC) found in semiconductor chips are used in a variety of applications such as computers, televisions, and cars to name just a few. IC can combine millions of transistors onto a single crystal silicon chip to perform complex data and store data. There has been a strong desire and significant advancement in shrinking the dimensions of IC thereby providing a greater number of functions in an ever smaller volume. An excellent example is the hand held calculator which initially could only perform simple mathematical functions but now can perform the most sophisticated mathematical modeling or statistical analysis at a fraction of the cost of the older models. Cost and size reduction are major factors driving this technology and no end seems in sight. Historically, such process improvements have resulted in roughly a 13% annual decrease in the minimum feature widths achievable for transistors mid interconnections.
With miniaturization comes an increased complexity of interconnect wiring used to transport data across a chip, Complex wiring patterns that can include multiple layers can be found in IC. The problem of electronic isolation of the individual circuits becomes significant since designs must deal with intralayer as well as interlayer effects. Electronic isolation has been accomplished by providing insulating or dielectric material between the circuit neighbors. Obviously as the dimensions shrink there is greater challenge to maintain electronic isolation.
In the conventional formation of conductive lines in an integrated circuit, a metal layer is deposited and patterned by conventional lithography and etching techniques to form metal lines/patterns, thus creating an uneven surface on the semiconductor material. In addition to finding suitable dielectric materials that will provide adequate electronic isolation, miniaturization has also created the problem of providing techniques that will adequately apply the dielectric, insulating material. The problem faced in this regard is that although the distances between circuitry lines is decreasing, the height of the circuitry lines formed by photolithographic means is not decreasing. This creates a situation where the dielectric material must be applied between tall, closely spaced features. Features with this topography are said to have high aspect ratios (height/width) and understandably it becomes very difficult to fill between those features.
It is often desirable for the insulating layer to be so formed that the upper surface of the insulating layer is planar over an extended region, irrespective of whether individual portions of the upper surface overlie metal lines or contacts or the spaces between such lines/contacts. The formation of such an insulating layer having a planar upper surface is referred to as planarization. Those skilled in the art know this insulating layer by many terms, such as, dielectric layer, gap filling layer, and passivation layer. All these terms are used interchangeably in this document and therefore should be construed to have the same meaning. It is especially important to have a planarized surface when additional circuitry is to be stacked in a multilayer design.
Although various processes have been available for forming insulating (gap filling) layers, chemical vapor deposition (CVD) was preferred since it seemed to meet the stringent requirements of filling high aspect channels between individual circuit lines. However, the temperatures that were required to perform this technique can be very high and lead to warping, distortion or other defects to metal line circuitry. In order to provide for etching or sputtering the technique of plasma generation was used to enhance CVD. Plasma deposition processes are of interest in this regard, because they may be able to form insulating layers of silicon dioxide or silicon nitride at relatively lower temperatures. In particular, high density plasma (HDP) processes, such as electron cyclotron resonance (ECR) processes and induced coupling plasma (ICP) processes have been found to produce high-quality silicon dioxide and silicon nitride layers. High density plasma (HDP) when combined with CVD provides for an HDP-CVD process such as plasma enhanced chemical vapor deposition (PECVD) that allows both simultaneous deposition and sputtering and is performed in an electron cyclotron resonance (ECR) apparatus. With this tool it is possible to vary the ratio of deposition to sputter etching. And although this technique can indeed be used at a lower temperature than conventional CVD it still causes unacceptably high temperatures at the early stages of gap filling when low deposition/sputter ratios (typically less than 4) are necessary to fill the high aspect ratio channels. This is especially noted for metallic lines composed of aluminum and its alloys such as aluminum copper. Temperatures as high as 400° C. have been observed and at these temperatures significant distortion of the metal features and circuitry can be observed. Aluminum contacts are intolerant of processing temperatures greater than about 350-400 C because at such temperatures “hillocks” tend to form in aluminum or aluminum alloy features.
The conventional HDP CVD process described hereinabove has a major drawback in that the high density plasma (HDP) deposition of the ECR oxide insulating layer often damages the underlying circuit elements, especially metal lines. High density plasma (HDP) sources employ magnetic fields and microwave power to create chemically active plasmas, preferably at very low gas pressures. It is difficult to control the energy transferred to the reactant ions in the plasma deposition. The high density plasma (HDP) chemical vapor deposition (CVD) process (e.g., ECR) is an in situ sputtering and deposition process using an argon flow, high microwave power and RF power. The deposition and sputtering steps are performed sequentially and are repeated until the proper coverage is obtained. When the metal lines on the wafers are subjected to in situ sputtering this creates a damaging “antenna effect”. The higher microwave power generates higher ion energy which increases the damage to the metal lines. The high power during the ECR oxidation process creates transconductance (i.e., gin) degradation due to the Fowler-Nordheim (F-N) tunneling stress. The defect that is readily observable is can be described as a hillock that protrudes above the surface of insulative layer and creating concurrently a void in the wall between the opposite side of the metal line and its adjacent insulative layer.
Therefore, there is still a need to create a structure and process whereby the damage to semiconductor devices, e.g., metal lines, from high density plasma (e.g. HDP and ECR) deposition of insulating layer is significantly reduced or eliminated.
Jain in U.S. Pat. No. 5,494,854, describes a gap-fill dielectric layer useful conductor lines that have low and high aspect channels separating the lines. In this invention HDP is used to assist in forming a dielectric layer that is specifically planarized in areas that cover high aspect conductor lines but necessarily between low aspect conductor lines. Furthermore, Jain does not teach the benefit of a pause time during the HDP process.
Wang et al. in U.S. Pat. No. 5,679,606, describe a process for forming a planar dielectric layer over metal lines using an in situ multi-step ECR de
Chien Hung-Ju
Dun Jowei
Tsan Chun-Ching
Wang Ying-Lang
Ackerman Stephen B.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Whitmore Stacy A
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