Low temperature grown optical detector

Details Low temperature grown optical detector Low temperature grown optical detector

2000-05-08

2003-11-25

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S448000

Reexamination Certificate

active

06653706

ABSTRACT:

NOMENCLATURE
1
. Processed SiIC
2
. Optional insulator layer
3
. HIII/V layer
4
. First electrode structure
5
. Light beam area
6
. Second electrode structure
7
. OD length
8
. OD width
9
. Insulating distance
10
. Second channel
11
. First channel
12
. HIII/V layer height
13
. Insulator height
14
. Gap width
15
. A/B/C light pulse duration
16
. A/B/C time-out interval
17
. A/B/C gating duration
18
. A/B/C extended duration
19
. A/B/C charging duration
20
. Carrier energy
21
. Gating voltage
22
. A/B/C time
23
. A/B/C light pulses
24
. A/B/C carrier energy levels
25
. A/B/C gating curves
26
. light intensity
27
. Operational value
28
. Gating level
1. Field of Invention
The present invention relates to the field of optical detectors grown on processed silicon based circuit structures.
2. Background of the Invention In modern computers the main processing load is handled by a number of silicon based integrated circuits (SiIC's) Those SiIC's are placed on boards that provide the electrical interconnections in the form of conductive traces. The boards are electrically connected to each other with connectors and wires.
Due to continuing development, the speed at which the SiIC's perform their logical operations is consistently rising. At the same time, more and more functions and features are provided by the computer, increasing the number and complexity of specific SiIC's that are brought into interaction with each other. As a result, the number of wires and traces, as well as their lengths, are also growing. Even though the signal speed outside the SiIC's is just a fraction of the internal speed, the amount and length of connectors, wires and channels, with their inductance and capacitance, impose a significant limitation on further development of faster SiIC's.
The logical operations within an SiIC are performed synchronously. For this reason, carefully designed channels have to provide all areas of the IC with clock signals. Distortions of the synchronous clock frequency are known as clock skew, which becomes more and more difficult to handle with increasing frequency and chip size. The clock signals are supplied to the SiIC via a peripheral junction and have to reach each destination over exactly the same distance. As a result, sophisticated channel distribution designs known as H-tree or fan-out designs occupy more and more space of the available SiIC area. In addition, the clock frequencies have reached levels at which local thermal differences affect the resistance and the travel speed of the clocking signal beyond acceptable tolerances. Furthermore, the placement of the clock channels partitions the SiIC and imposes a dimensional limitation on the design of the logical circuitry.
Optical data transmission bypasses the problems imposed by electrical wires and channels. Optical data transmission speed is highly independent of transmission distance and thermal influences. Other advantages include, for instance: no sensitivity to electronic noise, no capacitance or inductance in the transmission paths, no signal interference, vertical accessibility of SiIC's, and electric decoupling between individual electronic components.
A number of inventions provide for optical data transmission between SiIC's for data and signal communication as well as for distribution of clock signals. To utilize the advantages provided by optical data transmission to their utmost, it is essential to transform the optical signal into an electric signal as close as possible to the location of the logical operation. The devices that perform the transformation are called optical interconnects (OI's). They transform a received coherent light beam into a carrier energy with a distinct voltage or vice versa. In the specific form of a metal-semiconductor-metal detector (MSM-detector), the carrier energy is a gating voltage between two metallic electrodes. The conductivity created thereby is in approximate proportion to the intensity or energy of the received light beam. The efficiency of the transformation is defined by the ratio between the energies of the received light beam and that of the generated carrier energy. OI's can be either emitters or modulators, which convert an electrical signal into an optical signal, or optical detectors (OD), which convert a received optical signal into an electrical signal. A combination of both is also possible, even though the specific and differing tasks emitters and receivers have to perform lead more towards specifically designed and independently performing OD's.
U.S. Pat. No. 5,537,498 discloses an optical clock distribution system, whereby a bulky OD is brought into close proximity to the location of the logical operation within the SiIC. Conductive channels transmit the converted electrical clock signals from the OD to an electrical subsystem, wherein the clock signal is tuned and distributed over equalized fan-out paths to the final sites of the SiIC. The bulky design of the OD does not allow positioning close to the final destinations of the clock signals, which results in excessive lengths of conductive channels. Consequently, the clock signal has to be additionally tuned, which degrades the advantages achieved by optical clock distribution.
Another invention, disclosed in U.S. Pat. No. 5,568,574, presents modular-based photonic chip-to-chip interconnections for dense three-dimensional multichip module integration. A number of stacked SiIC's is thereby brought into signal communication by placing OD's on their opposing surfaces in congruent arrays, such that they can directly exchange optical signals. The OD's are pre-fabricated and flip chip bonded onto the processed SiIC. They are dimensioned far beyond the sizes required for their operational function in order to have sufficient size for physical placement and the mechanical robustness necessary for the bonding process. As a result, they have an unnecessarily high internal capacitance that has to be charged each time an optical signal is received and converted into an electrical signal. The response time of such an OI is relatively long, and a significant part of the converted electrical energy is consumed to charge the capacitance. Furthermore, the conductive state of an OD such as an MSM-detector fades over an extended time period, which causes the transmitted signal also to fade and to lose its crispness. In summary, the capacitance imposed by the bulky design of the OD degrades the signal coherence such that additional circuitry becomes necessary to compensate for this shortcoming.
Since logical operations are mainly performed within silicon-based IC's (SiIC's), there are attempts to also utilize Si-based materials for OD's. to integrate them together with the logical circuitry. The integration of OD's and logical circuitry in close proximity reduces the conductive path of the electric signal to the location of the logical operation to a minimum, and the capacitance in the channels is thereby kept at a very low level.
For example, U.S. Pat. No. 5,889,903 discloses a method and apparatus for distributing an optical clock in an integrated circuit. A coherent light beam is split and directed onto several OD's, which are distributed over the planar structure of an SiIC. The coherent light beam is pulsed with a clock frequency, which is synchronously converted in each of the OD's into a number of individual electrical clock signals. Hence, all logical circuits of the SiIC operate synchronously, driven by their individually derived clock signal. Unfortunately, the low efficiency of the SiOD's necessitates the use of amplifiers and buffers, which impose with their capacitance and subsequently with their time delay a latency onto the transmission path between the OI and the clock signal destination, and compromise the overall synchronicity in the SiIC.
Preferred materials for OI's with a high conversion efficiency are III-V compound materials (III-V) based, for instance, on Gallium-Arsenide (GaAs) or I

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