Semiconductor memory with nonvolatile memory cell array and...

Details Semiconductor memory with nonvolatile memory cell array and... Semiconductor memory with nonvolatile memory cell array and...

2001-09-21

2003-11-04

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S317000, C257S371000

Reexamination Certificate

active

06642569

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 USC 119 on Japanese Patent Application No. P2000-289129 filed on Sep. 22, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory having a nonvolatile memory cell array, and particularly, to the structure of source wiring in the memory cell array.
2. Description of the Related Art
Flash memories are roughly classified into NOR flash memories and NAND flash memories based on cell array structures. The NOR flash memories are randomly accessible and are appropriate for high-speed read applications.
FIG. 1
is a plan view showing a memory cell array in a NOR flash memory according to a first prior art. This prior art employs a SAS (self-aligned source) structure to reduce cell size. The SAS structure is formed by forming word lines (control gates
100
in FIG.
1
), removing an element isolation oxide film in a self-aligning manner with respect to the word lines, and forming a diffusion layer on the part where the oxide film has been removed. The diffusion layer forms drain regions
102
and source regions
104
.
FIGS. 2A and 2B
are sectional views taken along a line I—I of
FIG. 1
, in which
FIG. 2A
is before the removal of the element isolation oxide film
112
and
FIG. 2B
is after the removal of the same. The oxide film
112
is formed by LOCOS (localized oxidation of silicon) method. After the removal of the oxide film
112
, ions are implanted to form the diffusion layer
114
of n
+
-type.
A recently used element isolation method is STI (shallow trench isolation) method, which is effective to reduce a memory cell array. Applying the STI method to the memory cell array of
FIG. 1
causes a problem.
FIGS. 3A and 3B
are sectional views taken along the line I—I of
FIG. 1
assuming that the memory cell array of
FIG. 1
is formed by the STI method. Trenches are formed in a substrate
110
, and an insulating film is formed over the trenches. An element isolation region formed by the STI method is steeper than that formed with the element isolation oxide film
112
of
FIG. 2A
of the LOCOS method. In
FIG. 3A
, ions are vertically implanted into the substrate
110
, and no diffusion layer is formed on each side face of each trench from which an element isolation oxide film (not shown) has been removed. In
FIG. 3B
, ions are obliquely implanted into the substrate
110
. This may form an n
+
-type diffusion layer
116
on each trench side face, too. The structure of
FIG. 3B
, however, causes a problem shown in FIG.
4
B. Compared with a normal memory cell transistor of
FIG. 4A
, the structure of
FIG. 4B
involves a source region
104
having a very deep depth “d” due to horizontally diffused impurities. This results in increasing the resistance of the source region
104
and deteriorating read/write performance. To avoid the problem, the prior art must form metal source wiring connected to source regions
104
at predetermined intervals in parallel with bit lines. This source wiring increases a memory cell array area.
FIG. 5
shows a second prior art that employs an extended source region
104
, instead of the SAS structure. However, the extended source region
104
of
FIG. 5
increases a cell size Namely, a distance L
1
shown in
FIG. 6
must be long enough to absorb positioning errors in a lithography process, prevent variations in the shapes of channel regions, and avoid unstableness in memory cell characteristics, in particular, between vertically formed memory cells. A distance L
2
shown in
FIG. 6
must also be large enough to prevent a floating gate isolation region
128
from overlapping the source region
104
in the lithography process. If the overlapping happens, the source region
104
will be etched off in an etching process that follows the lithography process. It is difficult to maintain the shape of the island-shaped floating gate isolation region
128
. If there are positioning errors between the floating gate isolation regions
128
and control gates
100
to vary the shapes of the control gates
100
between even and odd lines, there will be large cell characteristic differences between the even and odd lines.
BRIEF SUMMARY OF THE INVENTION
An aspect of the present invention provides a nonvolatile semiconductor memory having a memory cell array. The memory cell array includes active regions extending linearly in parallel with one another and containing impurity diffused source and drain regions, element isolation regions extending linearly and isolating the active regions from one another, gate electrodes orthogonally crossing the active regions and element isolation regions and each having a floating gate and a control gate laid one upon another, and first metal conductors extending linearly in parallel with the gate electrodes and each connecting the source regions to one another between adjacent ones of the gate electrodes. The drain regions are connected via the first metal conductors or direct to a second metal conductors.


REFERENCES:
patent: 5293512 (1994-03-01), Nishigoori et al.
patent: 5295105 (1994-03-01), Atsumi
patent: 5736442 (1998-04-01), Mori
patent: 5850091 (1998-12-01), Li et al.
patent: 6060741 (2000-05-01), Huang
patent: 6201275 (2001-03-01), Kawasaki et al.
patent: 6240021 (2001-05-01), Mori
patent: 6355526 (2002-03-01), Furuhata
H. Watanabe, et al “Novel 0.44&mgr;m2 Ti-Salicides STI Cell Technology for High-Density NOR Flash Memories and High Performance Embedded Application” IEDM Technical Digest, 1998 pp. 975-978.

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