Low temperature formation of low resistivity titanium silicide

Details Low temperature formation of low resistivity titanium silicide Low temperature formation of low resistivity titanium silicide

1997-02-26

2001-02-13

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S683000, C438S660000

Reexamination Certificate

active

06187679

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and, more particularly, to a method for forming a titanium silicide layer overlying a silicon layer in an integrated circuit device where the phase transformation temperature of the titanium silicide has been reduced by the use of a refractory metal.
DESCRIPTION OF THE PRIOR ART
Titanium silicide has become the most widely-used silicide in the VLSI industry for self-aligned silicide applications because of its combined characteristics of low resistivity, the ability to be self-aligned, and relatively good thermal stability. Although TiSi
2
has certain advantages relative to other silicides, the fact that it is a polymorphic material presents additional problems in its use. Specifically, in typical use TiSi
2
exists as either an orthorhombic base-centered phase having 12 atoms per unit cell and a resistivity of about 60-90 micro-ohm-cm (known in the industry as the C49 phase), or as a more thermodynamically-favored orthorhombic face-centered phase which has 24 atoms per unit cell and a resistivity of about 12-20 micro-ohm-cm (known as the C54 phase). When using the generally-accepted processing conditions for forming titanium silicide, the less-desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature annealing step is required. This second step is disadvantageous because it can have detrimental effects on the silicide and other integrated circuit elements, especially at smaller line-widths. For example, the increasing use of dual-doped polysilicon gate structures in some devices has increased their sensitivity to additional heat cycles, as is required by the second anneal step. Also, silicon nitride peeling and cracking have been associated with the second annealing step.
The generally accepted set of processing conditions for forming titanium silicide includes: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at a temperature less than about 700° C., (4) selective etching, and (5) a phase transformation anneal at a temperature greater than about 700° C. It is the phase transformation anneal that converts the dominant C49 phase to the C54 phase. The initial formation temperature is kept below 700° C. in order to minimize over-spacer bridging. The second transformation anneal is performed after any un-reacted titanium has been selectively removed and is generally performed at temperatures of 50-200° C. above the formation temperature to insure full transformation to the C54 phase for best control of sheet resistance. However, as device line-widths and silicide film thicknesses continue to be scaled down, it becomes ever more desirable to eliminate the need for this second anneal step, as discussed further below.
It is generally accepted that the C49 phase forms first because of a lower surface energy than that of the C54 phase. In other words, the higher surface energy of the C54 phase forms a higher energy barrier to its formation. The second transformation anneal step used in the standard process above provides the additional thermal energy necessary both to overcome the nucleation barrier associated with forming the new surface and to grow the crystalline structure of the newly-forming C54 phase. In VLSI applications, if the phase transformation is inhibited or fails to occur uniformly, a degradation in circuit performance is observed. In some higher-performance circuits, the RC delay associated with a poor phase transformation is typically about 5-10 percent.
A significant limitation on the C49-to-C54 phase transformation is a phenomenon known as agglomeration. If the thermal energy used to obtain the phase transformation is excessive, then a morphological degradation of the titanium silicide results, which is commonly referred to as agglomeration. As line-widths and silicide film thicknesses decrease, the thermal energy required to effect the C49-to-C54 phase transformation increases, yet the thermal energy level at which the silicide film starts to agglomerate decreases. Thus, there is an ever-shrinking process window for performing this phase transformation, making process control and uniformity more difficult to achieve.
Thus, there is a need for an improved method for forming the C54 phase of titanium silicide without requiring a second high-temperature annealing step, as in the generally-accepted process above. Eliminating the second annealing step or reducing the temperature necessary to transform the C49 phase to the desired C54 phase titanium silicide would reduce the problems associated with high temperature processing and the limitations resulting from agglomeration of silicide films during the phase transformation anneal.
SUMMARY OF THE INVENTION
This need is satisfied, the limitations of the prior art overcome, and other benefits realized in accordance with the principles of the present invention by a method for forming a metal silicide overlying a silicon layer on a semiconductor wafer. The method includes forming a titanium silicide layer on a silicon substrate of a semiconductor device, comprising: (1) depositing a titanium alloy layer over a silicon substrate wherein the titanium alloy comprises from 1 to 20 atomic percent refractory metal; and (2) heating the titanium alloy to a temperature sufficient to substantially form C54 phase titanium silicide from the titanium alloy. This temperature may be less than about 700° C.
In one application of the above method the titanium alloy may comprise from 1 to 15 atomic percent refractory metal and the refractory metal may comprise one or more of the group consisting of Ta, Nb, Mo, W, V and Cr. The titanium alloy may comprise titanium, silicon and a refractory metal; an example being TiSi
2
and a refractory metal. The semiconductor substrate may be selected from monocrystalline silicon, polycrystalline silicon, amorphous silicon, a silicon germanium alloy, silicon on insulator containing N-type dopant and silicon on insulator containing P-type dopant. The titanium alloy may be deposited over the silicon substrate by physical vapor deposition or chemical vapor deposition.
Another aspect of the invention includes a semiconductor device having a C54 phase titanium silicide layer comprising: (1) a silicon layer; and (2) a layer of titanium silicide over said silicon layer wherein said layer titanium silicide comprises substantially C54 phase titanium silicide and from 1 to 20 atomic percent refractory metal. A further aspect of the semiconductor device of the present invention includes a silicon layer selected from the group of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium alloy, silicon on insulator having N-type dopant and silicon on insulator having P-type dopant. The semiconductor device of the present invention may include titanium silicide layer comprising from 1 to 15 atomic percent refractory metal and a thickness of between 10 to 200 nm.


REFERENCES:
patent: 5880505 (1999-03-01), Fujii et al.
patent: 6022801 (2000-02-01), Domenicucci et al.
Y. Dao, et al. “Structural and Electronic Properties of (Ti0.9Zr0.1)Si2 thin films on Si(111)”, Applied Physics Letters, vol. 65, No. 19, pp. 2413-2415, Nov. 1994.
Y. Dao, et al. “Phase Stabilities and Surface Morphologies of (ti1-xZrx)Si2 thin films on Si(100)”, Journal of Applied Physics, vol. 78, No. 11, pp. 6564-6591, Nov. 1994.

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