Low-stress method of fabricating field-effect transistors having

Details Low-stress method of fabricating field-effect transistors having Low-stress method of fabricating field-effect transistors having

1995-12-05

1997-12-30

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438197, 438230, H01L 2184

Patent

active

057029865

ABSTRACT:
This invention is a process flow involving wordline spacer formation and source/drain implants which mitigates stress-induced damage to the silicon substrate during the post-implant anneal step. The process employs composite wordline spacers having a removable silicon dioxide portion and a non-removable silicon nitride portion. The post-implant anneal step is performed with only the silicon nitride portion of the spacer in place on the wordlines. The thinness of the silicon nitride portion greatly reduces the stress levels experienced by the substrate during the anneal as compared with that experienced by the substrate when thick one-piece silicon nitride spacers are left in place during the anneal.

REFERENCES:
patent: 5015595 (1991-05-01), Wollesen
patent: 5102816 (1992-04-01), Manukonda et al.
patent: 5244823 (1993-09-01), Adan
patent: 5298446 (1994-03-01), Onishi et al.
patent: 5424234 (1995-06-01), Kwon
patent: 5641698 (1997-06-01), Lin

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