Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-08-28
2001-05-29
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S330000, C257S331000, C257S332000, C257S334000, C257S341000, C257S342000, C438S206000, C438S212000
Reexamination Certificate
active
06239463
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to power MOSFETs and in particular to power MOSFETs in which an important criterion of performance is the resistance of the MOSFET when it is turned on.
BACKGROUND OF THE INVENTION
The resistance of a vertical power MOSFET has several components: the resistance of the channel, the resistance beyond the channel where the current is spreading out, the resistance in a relatively lightly-doped epitaxial layer which is normally a part of these devices, and the resistance of the heavily-doped substrate. In addition, vertical double-diffused (DMOS) devices with planar channels (known as planar VDMOS) have an additional component of resistance that is due to the crowding of the current between the depletion regions that surround the body regions.
FIGS. 1-11
illustrate several aspects of these resistance components.
FIGS. 1 and 2
show cross-sectional views of two classes of vertical MOSFETs each of which includes an N-epitaxial (epi) layer
12
which is grown on an N+ substrate
11
, which functions as the drain.
FIG. 1
shows a planar DMOS
10
including P-body regions
13
, P+ body contact regions
14
, and N+ source regions
15
. A gate
16
is formed over the top surface of the epi-layer
13
and is separated from the top surface by an oxide layer
17
. The N+ source regions
15
are contacted by a metal layer
28
which also forms a short between the N+ source regions
15
and the P+ body contact regions
14
and thereby prevents the parasitic NPN bipolar transistor from turning on. As shown by the arrows, when the device is turned on current flows from the N+ source regions
15
, laterally through channel regions in the P-body regions
13
and then downward through the N-epi layer
12
to the N+ substrate
11
(drain).
MOSFET
20
shown in
FIG. 2
is a trench-gated MOSFET in which a gate
26
is formed in a trench and is separated from the N-epi layer
12
by an oxide layer
27
. The gate trenches typically form a lattice or array of cells which in
FIG. 2
includes a MOSFET cell
29
and a diode cell
30
. MOSFET cell
29
includes a P-body region
23
, a P+ body contact region
24
, and an N+ source region
25
. N+ source region
25
and P+ body contact region
24
are contacted and shorted together by a metal layer
28
. As shown by the arrows, when the device is turned on currents flow from the N+ source region
25
downward through channel regions adjacent the walls of the trenches, through the N-epi layer
12
and into the N+ substrate (drain).
Diode cell
30
includes a deep P+ diffusion
31
which ensures that voltage breakdown occurs away from the trench walls. Impact ionization near the trench walls could cause hot carriers to be injected into and damage the gate oxide
27
. Preferably there is a diode cell for a given number of MOSFET cells as taught in application Ser. No. 08/459,555, filed Jun. 2, 1995, which is incorporated herein by reference. Alternatively, the deep P+ diffusion could be included within the MOSFET cell
29
as taught in U.S. Pat. No. 5,072,266 to Bulucea et al.
As the carriers (electrons) drift through the N-epi layer
12
in MOSFETs
10
and
20
a voltage develops across N-epi layer
12
(sometimes referred to as a “drift” region). The magnitude of this voltage depends on the thickness of and dopant concentration in N-epi layer
12
, which are normally chosen in a compromise to provide a variety of features and characteristics for the device. In particular the thickness and dopant concentration are selected to provide a particular blocking voltage when the device is turned off. Generally speaking, the lower the dopant concentration and the thicker the N-epi layer
12
(between the top interface of the N+ substrate
11
and a P-type region), the higher the blocking voltage. In
FIG. 1
X
epi
(off) designates the vertical distance between the N+ substrate
11
and the lower boundary of P-body region
13
, and in
FIG. 2
X
epi
(off) designates the vertical distance between the N+ substrate
11
and the lower limit of deep P+ diffusion
31
. In each case X
epi
(off) represents the thickness of N-epi layer
12
that must support the voltage across the device when it is turned off. Note also in
FIGS. 1 and 2
that X
jB
designates the level of the lower junction of the P-body regions
13
,
23
relative to the surface of the epi-layer, which is labeled zero. In
FIG. 1
X
jB
coincides with the beginning of X
epi
; in
FIG. 2
X
epi
(off) is not referenced to X
jB
.
The cross-sections AA′ in FIG.
1
and CC′ in
FIG. 2
correspond to diodes which are formed at the junction of N-epi layer
121
and P-body region
13
and deep P+ diffusion
31
, respectively. The cross-sections BB′ and DD′ designate the regions in which the current flows vertically through the N-epi layer
12
.
The diodes at cross-sections AA′ and CC′ are represented generally by a diode
32
on the left side of
FIG. 3
which shows a P or P+ region
33
, an N+ region
35
and an intervening N-epi layer
34
(referred to as a PN or PIN avalanche clamp). The thickness of the N-epi layer
34
is designated X
epi
(net). The right side of
FIG. 3
shows a graph of the strength of the electric field (E=dV/dx) in the diode
32
. The electric field reaches a peak at the junction of P or P+ region
33
and N-epi layer
34
and then drops with increasing depth. If N-epi layer
34
is relatively heavily doped, the electric field (curve labeled PN) drops over a short distance; if N-epi layer
34
is lightly doped the electric field (curve labeled PIN(reachthrough)) is relatively flat indicating that the depletion region extends all the way to N+ substrate
35
; if N-epi layer
34
is doped to an intermediate level the electric field (curve labeled P&ngr;N(reachthrough)) the depletion region again reaches through the entire N-epi layer
34
but the electric field is not flat across the entire layer
34
. Rather, in the last case the electric field slopes to some degree until it reaches the N+ region
35
. Neither the P or P+ region
33
nor the N+ region
35
can support any significant electric field. Since the breakdown voltage is roughly equal to the integral of the electric field over the interval X
epi
(net), it is apparent that the area under the triangle or trapezoid gives a rough estimate of the voltage of the device.
Thus if the N-epi-layer
34
is made thinner or doped more heavily, the breakdown voltage is reduced. On the other hand, a thinner, more heavily doped epi layer has a lower resistance when the device is turned on. A variety of techniques have been used to optimize the device by fabricating the thinnest possible, most heavily doped epi-layer that still provides an adequate breakdown voltage. All of these variations are only a few percentage points apart in terms of what is needed to provide the optimal doping/thickness combination to meet and support the required breakdown voltage.
FIG. 4
illustrates a graph that is available from many sources showing the “reach-through” breakdown voltage of a PIN diode as a function of the “background” doping concentration of the intermediate layer (C
B
) for various intermediate layer thicknesses (designated as W
EPI
, which in this particular publication is equivalent to X
epi
(off) in FIGS.
1
and
2
). The graph of
FIG. 4
is taken from Semiconductor Technology Handbook, Technology Associates, page 8-9 (1980). If W
EPI
is an infinite thickness, there is a one-to-one correspondence between the background dopant concentration and the breakdown voltage. Since
FIG. 4
is plotted on log-log paper, this implies a strong dependence between the dopant concentration and breakdown voltage. If the background concentration is increased two orders of magnitude from 10
15
cm
−3
to 10
17
cm
−3
, for example, the breakdown voltage falls from about 300 V to about 15 V. If the intermediate layer is made th
Cornell Michael E.
Darwish Mohamed
Grabowski Wayne
Williams Richard K.
Mintel William
Siliconix incorporated
Skjerven Morrill & MacPherson LLP
Steuber David E.
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