Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-03-08
2008-11-04
Pham, Thanh V. (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S682000
Reexamination Certificate
active
07445996
ABSTRACT:
A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide in contact structures of the peripheral logic circuitry areas and physical vapor deposition to provide a metal mode (metallic) titanium layer in contact with the poly plugs in the memory cell array area of a semiconductor device, for example, a DRAM memory device according to the present invention. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the present of titanium silicide, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.
REFERENCES:
patent: 5674773 (1997-10-01), Koh et al.
patent: 5837577 (1998-11-01), Cherng
patent: 5893734 (1999-04-01), Jeng et al.
patent: 5990021 (1999-11-01), Prall et al.
patent: 6124164 (2000-09-01), Al-Shareef et al.
patent: 6180508 (2001-01-01), Lowrey
patent: 6335282 (2002-01-01), Sharan et al.
patent: 6455424 (2002-09-01), McTeer et al.
patent: 6580115 (2003-06-01), Agarwal
patent: 6703306 (2004-03-01), Lee
patent: 6756267 (2004-06-01), Shimizu et al.
patent: 6780758 (2004-08-01), Derderian et al.
patent: 6784501 (2004-08-01), Lane et al.
patent: 2001/0005058 (2001-06-01), Asano et al.
patent: 2002/0042209 (2002-04-01), Abe et al.
patent: 2006/0046398 (2006-03-01), McDaniel et al.
Fazio, Al, et al.; ETOX™ Flash Memory Technology: Scaling and Integration Challenges; Intel Technology Journal—Semiconductor Technology and Manufacturing; May 16, 2002; pp. 23-30; vol. 06, Issue 02.
Tao, K., et al.; Ionized Physical Vapor Deposition of Titanium Nitride: A Global Plasma Model; Journal of Applied Physics; Apr. 1, 2002; pp. 4040-4048; vol. 91; No. 7.
Mao, D., et al.; Ionized Physical Vapor Deposition of Titanium Nitride: Plasma and Film Characterization; J. Vac. Sci. Technol. A 20(2); Mar./Apr. 2002; pp. 379-387.
Dismore & Shohl LLP
Micro)n Technology, Inc.
Nguyen Khiem D.
Pham Thanh V.
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