Low resistance ground wiring in a semiconductor device

Details Low resistance ground wiring in a semiconductor device Low resistance ground wiring in a semiconductor device

1997-11-05

2000-06-06

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, H01L 21336

Patent

active

060717858

ABSTRACT:
There is provided a method of fabricating a semiconductor device, including the steps of (a) forming a first insulating film on a semiconductor substrate, (b) forming gate electrodes on the first insulating film, the gate electrodes having a two-layered structure including a first conductive film and a second insulating film lying over the first conductive film, (c) forming a diffusion layer around the gate electrodes, (d) forming an insulating sidewall film around a sidewall of the gate electrodes, (e) covering a resultant with a third insulating film, (f) forming a contact hole between the gate electrodes in self-aligning fashion, (g) covering a resultant with a second conductive film, (h) covering a resultant with a fourth insulating film, (i) planarizing the fourth insulating film, (j) isotropically etching the planarized fourth insulating film to make a part of the second conductive film to appear, (k) covering a resultant with a third conductive film, and (l) etching the third conductive film, the fourth insulating film and the second conductive film in a selective area to form a ground wiring layer. The above mentioned method makes it possible to form a contact hole in self-aligning fashion and further to form a low resistance ground wiring.

REFERENCES:
patent: 5330929 (1994-07-01), Pfiester et al.
patent: 5413961 (1995-05-01), Kim
patent: 5439840 (1995-08-01), Jones, Jr. et al.
patent: 5693554 (1997-12-01), Lee
patent: 5759890 (1998-06-01), Chao

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