Low resistance contact semiconductor device structure

Details Low resistance contact semiconductor device structure Low resistance contact semiconductor device structure

2005-10-31

2008-10-21

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S592000, C257SE21630

Reexamination Certificate

active

07439123

ABSTRACT:
A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source and drain regions, disposing a second metallic layer on the first metallic layer; doping the first metallic layer with a first dopant through a portion of the second metal layer disposed over the second gate with spacers; and then heating the intermediate structure to a temperature and for a time sufficient to form a silicide of the first metallic layer. This first layer is, for example, Ni while the second layer is, for example, TiN.

REFERENCES:
patent: 5217924 (1993-06-01), Rodder et al.
patent: 5258637 (1993-11-01), Sandhu et al.
patent: 5593923 (1997-01-01), Horiuchi et al.
patent: 5624867 (1997-04-01), Cheng et al.
patent: 5654241 (1997-08-01), Kakumu
patent: 5891784 (1999-04-01), Cheung et al.
patent: 5899741 (1999-05-01), Tseng et al.
patent: 6069044 (2000-05-01), Wu
patent: 6156615 (2000-12-01), Kepler
patent: 6232220 (2001-05-01), Penka et al.
patent: 6242312 (2001-06-01), Huang et al.
patent: 6319785 (2001-11-01), Ha et al.
patent: 6387803 (2002-05-01), Talwar et al.
patent: 6492264 (2002-12-01), Oda
patent: 6746944 (2004-06-01), Xiang et al.
patent: 6930030 (2005-08-01), Rausch et al.
patent: 2002/0098689 (2002-07-01), Chong et al.
patent: 2002/0102805 (2002-08-01), Cheng et al.
Jeong Su Han et al., “Improvement of P+ Contact Resistance through Optimal Boron Distribution on TiSi2/ P+ Interface for 0.18 μm DRAM Technology and beyond”, IEEE, 2000, pp. 83-86.
S.M. Sze, ed., “VLSI Technology, Second Edition”, New Jersey: McGraw-Hill Publishing Company, 1988, pp. 362-365 (attention to paid to p. 365, first complete paragraph).

Affiliated with

Also associated with

Rating

Low resistance contact semiconductor device structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low resistance contact semiconductor device structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low resistance contact semiconductor device structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4010047