Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-02-28
2004-05-25
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06742150
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The subject matter of the application relates to a module having an integrated circuit in accordance with a customer requirement (ASIC) with devices, associated with its connections, for receiving or transmitting electrical signals, in particular boundary scan devices in accordance with IEEE Standard 1149.1a for test purposes, which is equipped with the number of connections required for the specified functions of the module.
2. Description of the Related Art
Application specific modules ASIC (application specific integrated circuits) are used to solve customer-specific circuitry problems.
Application specific modules ASIC, which have boundary scan devices in accordance with IEEE Standard 1149.1a are known in principle from Elektronik 23/1997, pages 114 to 122.
If a given application specific module ASIC is intended to be adapted to different requirements, then, conventionally, the modification process requires a complete design, layout and test phase.
SUMMARY OF THE INVENTION
The present invention is directed to reducing the effort in terms of development costs and time for modification of a customer specific module, in particular in the event of only minor design corrections.
In the case of an object as outlined by the features of the precharacterizing clause, the problem is solved by providing free connections, in addition to the number of required connections. Boundary scan devices are being allocated to these free connections.
The subject matter of the application has the following advantages:
No changes to the boundary scan logic, wiring at the top levels insertion of input-output buffers, or simulations relating to them are required for new connections (pins), since the reserved pins can be used.
There is no need to produce a new BSDL (boundary scan description language) file or to generate a new boundary scan test.
No new pinning definitions with the ASIC manufacturers.
No change to the NAND tree.
No change relating to the clock tree or SSO (Simultaneously Switching Outputs).
The probability of errors in the redesign is considerably reduced, since less is changed. (Less change=>fewer errors).
The documentation relating to pins, JTAG, (for example BSDL) remains to the same standard.
The emulation of the redesign is simplified, since no new pins occur.
The ASIC manufacturers offer changes to a customer specific module, which changes are limited to the metallization level more cost-effectively than if new logic elements had to be incorporated and it was necessary to interfere with the overall layout; the present invention offers the capability to change the logic function by changing the internal wiring, which can be carried out cost-effectively using a change capability which is limited to the metallization level,
The probability of being able to carry out a redesign in this cost-saving and time-saving manner is considerably increased.
REFERENCES:
patent: 5515505 (1996-05-01), Ishizuka
patent: 5544174 (1996-08-01), Abend
patent: 5805609 (1998-09-01), Mote, Jr.
patent: 0 639 006 (1995-02-01), None
A. Auer, et al., “Schaltungstest mit Boundary Scan”, Heidelberg: Huthig-Verlag, (1996) pp. 107f, 118-125, 130f.
The Institute of Electrical and Electronics Engineers: IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-1990, New York, (1990), pp. 1-3. (one sheet-double sided).
Korus, R., et al., “Boundary-Scan: Status und neue Applikationen”, In: Elektronik, (1997) vol. 23, pp. 114-122.
Ghameshlu Majid
Krause Karlheinz
Chase Shelly A
De'cady Albert
Siemens Aktiengesellschaft
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