Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1994-07-07
1995-10-24
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Data refresh
365194, G11C 700
Patent
active
054615909
ABSTRACT:
A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.
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Zhu, "Ultrastable Integrated CMOS Oscillator," International Journal of Electronics, vol. 70, No. 2, pp. 433-444, Feb. 1991, London, GB.
Abstract of Japanese patent document JP 22046088, Dec. 20, 1990.
Cordoba Michael V.
Hardee Kim C.
Manzo Edward D.
Nelms David C.
Nippon Steel Semiconductor Corp.
United Memories Inc.
Zarabian A.
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