Low power tri-level decoder circuit

Details Low power tri-level decoder circuit Low power tri-level decoder circuit

2006-08-08

2006-08-08

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Three or more active levels

With conversion

C326S106000, C327S416000

Reexamination Certificate

active

07088139

ABSTRACT:
A tri-level decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is configured to compare an input voltage to a first threshold, and the second decoder circuit is configured to compare the input voltage to a second threshold. The first decoder circuit is configured to provide substantially no current to a current mirror if the input voltage is less than the first threshold, and to provide a current to the current mirror otherwise. The current mirror is configured to reflect the current to provide a reflected current. A current source is configured to pull down a first output node to a first logic level if the reflected current is substantially zero. The current mirror is configured to drive the first output node to a second logic level otherwise. The second decoder circuit may operate similarly.

REFERENCES:
patent: 5457411 (1995-10-01), Hastings
patent: 5610537 (1997-03-01), Hastings
patent: 6201378 (2001-03-01), Eto et al.
patent: 6472907 (2002-10-01), Setogawa
patent: 6700416 (2004-03-01), Cowles
patent: 6864725 (2005-03-01), Cowles et al.

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