Low-power static column redundancy scheme for semiconductor...

Details Low-power static column redundancy scheme for semiconductor... Low-power static column redundancy scheme for semiconductor...

2002-03-06

2003-08-05

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189070, C365S189120, C365S225700

Reexamination Certificate

active

06603690

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a low-power static column redundancy scheme for semiconductor memory chips, more specifically for embedded memory chips such as dynamic random access memories (eDRAM), and more particularly pertains to a low-power static column redundancy scheme for a wide data-width eDRAM macro which uses existing eDRAM hardware and eliminates unnecessary power consumption.
2. Discussion of the Prior Art
The present invention has applicability to many different types of semiconductor memory chips, although the following discussion and the exemplary embodiments herein concern embedded dynamic random access memories (eDRAM) in particular.
Embedded dynamic random access memories (eDRAM) with wide data width have been proposed to replace static random access memories (SRAM) for high-speed data access in L2 cache applications. Since each DRAM cell has only one transistor and one capacitor, compared to an SRAM cell that has six transistors, the size of an eDRAM cache can be significantly smaller than the size of an SRAM cache. In order to reduce the data access time, eDRAM arrays are typically fabricated as a plurality of small arrays called microcells. Each microcell usually contains 64 to 256 word lines and 64 to 256 bit-line pairs, and is 16× to 256× smaller than a bank of a stand-alone DRAM, which typically has 1,024 word lines and 1,024 bit-line pairs. Since each eDRAM array operation only requires one microcell to be activated, the lighter loading of word lines and bit lines in a microcell can significantly improve the data access speed.
The large size of an eDRAM macro often requires the use of a small SRAM macro as the cache interface between the eDRAM and the processor for data read/write operations. A wide internal bus is provided to transfer data among the eDRAM, the SRAM, and the processor. A small TAG memory may also be added to record the microcell address of the data stored in the SRAM. Since all the data along a selected word line are retrieved, no additional column decoding is necessary.
One of the key challenges in the design of a wide data-width eDRAM is to provide an effective column redundancy scheme to fix defective column elements. In a conventional DRAM array, bit-line pairs are hierarchically grouped by the column addresses. Since the data are selected from only one group of bit-line pairs each time, the most common column redundancy scheme uses the existing column address and repairs the entire group of bit-line pairs. However, for a wide data-width eDRAM design, all the bit lines from the eDRAM macro are simultaneously fed into the SRAM, and all the data lines from the SRAM are directly fed into the processor. It is difficult to identify and fix the failed bit lines without significantly increasing the chip size.
Two column redundancy schemes have been recently proposed for a wide data-width eDRAM:
[1] A dynamic redundant column swapping scheme was proposed in YOR8-2000-1212, entitled “Column Redundancy Scheme for Wide Bandwidth Embedded DRAM.” In this disclosure, the incoming addresses in each cycle are compared to the addresses of failed components stored in the fuse bank. If a match is found, an internal column address is created and used to perform the column redundancy swapping operation. The address matching and redundancy swapping operations can be done in a pipeline cycle with high speed, but its high power consumption makes it unsuitable for low-power applications such as hand-held and portable devices.
[2] A dynamic redundant microcell swapping scheme was proposed in YOR8-2001-0001, entitled “A New Microcell Redundancy Scheme for High Performance eDRAM.” Instead of swapping the defective word lines and bit lines, the entire microcell is replaced, which requires the size of each microcell to be small and the number of micro cells to be large. Since the dynamic replacement scheme for microcell swapping is similar to column swapping, it also consumes a lot of power and is not suitable for low-power applications.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a low-power static column redundancy scheme for semiconductor memory chips.
A more specific object of the subject invention is the provision of a low-power, static column redundancy scheme for a wide data-width eDRAM macro by using existing eDRAM hardware and eliminating unnecessary power consumption.


REFERENCES:
patent: 5636227 (1997-06-01), Segars
patent: 5677917 (1997-10-01), Wheelus et al.
patent: 6081910 (2000-06-01), Mifsud et al.
patent: 6292422 (2001-09-01), Pitts
Yasuhara Sato, et al. (1998) “Fast Cycle RAM (FCRAM); a 20-ns Random Row Access, Pipe-Lined Operating DRAM”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 22-25.
Yoshinori Okajima, et al. (2000) “An 0.18um Embedded FCRAM ASIC with DRAM Density and SRAM Performance”, IEEE, pp. 37-39.

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