Low power scan testing techniques and apparatus

Details Low power scan testing techniques and apparatus Low power scan testing techniques and apparatus

2011-04-12

2011-04-12

Raymond, Edward (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Signal generation or waveform shaping

Reexamination Certificate

active

07925465

ABSTRACT:
Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.

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