Low power pre-silicide process in integrated circuit technology

Details Low power pre-silicide process in integrated circuit technology Low power pre-silicide process in integrated circuit technology

2006-05-23

2006-05-23

Owens, Douglas W (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S382000

Reexamination Certificate

active

07049666

ABSTRACT:
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

REFERENCES:
patent: 6531750 (2003-03-01), Chan et al.
patent: 2005/0032393 (2005-02-01), Weimer

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