Low power manager for standby operation of memory system

Details Low power manager for standby operation of memory system Low power manager for standby operation of memory system

2006-05-16

2006-05-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Powering

Data preservation

C365S226000

Reexamination Certificate

active

07046572

ABSTRACT:
A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

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