Low power, high performance latching interfaces for converting d

Details Low power, high performance latching interfaces for converting d Low power, high performance latching interfaces for converting d

1995-03-24

1997-07-22

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 95, 327203, 327211, H03K 1900, H03K 19096

Patent

active

056507356

ABSTRACT:
A circuit (51) for converting a pair of precharged dynamic logic signals into a static logic signal includes a first input (61) to receive one of said dynamic logic signals, a second input (67) to receive the other of said dynamic logic signals, and an output (Qout). A first signal path from said first input to said output includes only two logic gates (63,69), and a second signal path from said second input to said output includes only one logic gate (69).

REFERENCES:
patent: 4914318 (1990-04-01), Allen
patent: 5025174 (1991-06-01), Shikata
patent: 5257223 (1993-10-01), Dervisoglu
patent: 5426380 (1995-06-01), Rogers

Affiliated with

Also associated with

Rating

Low power, high performance latching interfaces for converting d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power, high performance latching interfaces for converting d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power, high performance latching interfaces for converting d will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1562386