Low power flash memory devices

Details Low power flash memory devices Low power flash memory devices

2008-05-13

2008-05-13

Ngô, Ngân V. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S378000, C257SE29129, C257SE29300, C257SE21422, C257SE21680

Reexamination Certificate

active

07372098

ABSTRACT:
A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a floating gate of the cells.

REFERENCES:
patent: 3893151 (1975-07-01), Bosselaar et al.
patent: 5867425 (1999-02-01), Wong
patent: 5896315 (1999-04-01), Wong
patent: 5926418 (1999-07-01), Wong
patent: 5940324 (1999-08-01), Chi et al.
patent: 6060742 (2000-05-01), Chi et al.
patent: 6091635 (2000-07-01), Chi et al.
patent: 6160286 (2000-12-01), Chi
patent: 6252799 (2001-06-01), Liu et al.
patent: 6326265 (2001-12-01), Liu et al.
patent: 6586797 (2003-07-01), Forbes et al.
patent: 6624026 (2003-09-01), Liu et al.
patent: 6721204 (2004-04-01), Yeh et al.
patent: 6734490 (2004-05-01), Esseni et al.
patent: 6778441 (2004-08-01), Forbes et al.
patent: 6794255 (2004-09-01), Forbes et al.
patent: 6980471 (2005-12-01), Samachisa
patent: 7045430 (2006-05-01), Ahn et al.
patent: 7125772 (2006-10-01), Wong
patent: 7157769 (2007-01-01), Forbes
patent: 7160577 (2007-01-01), Ahn et al.
patent: 7198999 (2007-04-01), Forbes et al.
patent: 2002/0027804 (2002-03-01), Wong
patent: 2002/0110033 (2002-08-01), Forbes
patent: 2003/0048666 (2003-03-01), Eldridge et al.
patent: 2003/0049900 (2003-03-01), Forbes et al.
patent: 2004/0061168 (2004-04-01), Cappelletti et al.
patent: 2004/0114433 (2004-06-01), Forbes
patent: 2005/0194633 (2005-09-01), Mori
patent: 2005/0277243 (2005-12-01), Forbes
patent: 2006/0139998 (2006-06-01), Samachisa
patent: 2006/0140009 (2006-06-01), Lojek
Bude, J. D., et al., “EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writing”,International Electron Devices Meeting, Technical Digest, (Dec. 1995), 989-991.
Bude, J. D., et al., “Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35 micrometer and Below”,International Electron Devices Meeting, Technical Digest, Held in Washington, D.C., (Dec. 7-10, 1997), 279-282.
Han, K. M., et al., “Sequential substrate and channel hot electron injection to separate oxide and interface traps in n-MOSTs”,Solid-State Electronics, vol. 38, No. 1, (1995), 105-113.
Mahapatra, S. , et al., “Chisel Flash EEPROM—Part I: Performance and Scaling”,IEEE Transactions on Electron Devices, vol. 49, No. 7, (Jul. 2002), 1296-1301.
Mahapatra, S. , et al., “Chisel Flash EEPROM—Part II: Reliability”,IEEE Transactions on Electron Devices, vol. 49, No. 7, (Jul. 2002), 1302-1307.
Neugroschel, Arnost , et al., “Direct-Current Measurements of Oxide and Interface Traps on Oxidized Silicon”,IEEE Transactions on Electron Devices, vol. 42, No. 9, (1995), 1657-1662.
Nishida, Toshikazu , “BiMOS and SMOSC structures for MOS parameter measurement”,Solid-State Electronics, vol. 35, No. 3, (Mar. 1992), 357-369.
Sonoda, Ken'Ichiro , et al., “Compact Modeling of a Flash Memory Cell Including Substrate-Bias-Dependent Hot-Electron Gate Current”,IEEE Transactions on Electron Devices, vol. 51, No. 10, (Oct. 2004), 1726-1730.

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