Low power dynamic random access memory

Details Low power dynamic random access memory Low power dynamic random access memory

1996-12-17

1998-01-20

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

365202, G11C 700

Patent

active

057107386

ABSTRACT:
A low power dynamic random access memory (DRAM) is disclosed. The DRAM includes an equalization circuit connected to a pair of bitlines for allowing electric charge of the bitline having higher voltage to flow to the bitline having lower voltage. This equalization circuit is activated by a first precharge control signal. A delay circuit is used to generate a second precharge control signal, which is the delayed signal of the first precharge control signal. This precharge control circuit is connected to the bitlines and to a constant voltage source for setting the voltages on the bitlines to the voltage of the constant voltage source in response to the second precharge control signal. A sense amplifying circuit is connected to the pair of bitlines to amplify the voltages of the bitlines so that the voltage of one bitline is complementary to the voltage of the other bitline.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 5062079 (1991-10-01), Tsuchida
patent: 5177708 (1993-01-01), Furutani
patent: 5243574 (1993-09-01), Ikeda
patent: 5321657 (1994-06-01), Arimoto

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