Low power data storage element with enhanced noise margin

Details Low power data storage element with enhanced noise margin Low power data storage element with enhanced noise margin

2005-10-11

2005-10-11

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S104000, C327S202000, C327S203000

Reexamination Certificate

active

06954086

ABSTRACT:
A data storage element for use in LSSD compliant circuit designs. The data storage element has an alternate, or scan, data input circuit that has increased immunity to electrical noise while maintaining lower power consumption than the circuits used for primary data input. This increased noise immunity reduces the probably that noise on the alternate data input will cause an unintended change of data state stored in the data storage element. Modification of latch circuits used in the data storage element allow a reduction in the number of transistors used in the latch circuits, thereby compensating for the increase in transistors used in the alternate data input circuit and allowing the data storage element to use the same number of transistors as prior designs that have less noise immunity on their alternate data inputs.

REFERENCES:
patent: 5793944 (1998-08-01), Luick
patent: 5875346 (1999-02-01), Luick
patent: 6065107 (2000-05-01), Luick
patent: 6127867 (2000-10-01), Coughlin et al.
patent: 6320419 (2001-11-01), Burda et al.
patent: 6348825 (2002-02-01), Galbi et al.

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