Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-05-06
2004-09-21
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S063000, C365S189011, C365S226000
Reexamination Certificate
active
06795361
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices, such as dynamic random access memory (DRAM) devices, having row-to-column shorts. In particular, it relates to memory devices having low power consumption after acquiring such shorts and to the methods for achieving such low power consumption.
BACKGROUND OF THE INVENTION
DRAM devices are a well known type of high-density semiconductor memory used for primary storage (as compared to secondary storage, such as a disk drive) and are often chosen over other memories because of its relative low cost. In exchange for low cost, however, DRAM devices are slower than Static RAM devices, for example, and require periodic refresh operations.
As is known, a DRAM is arranged in an array of rows (often referred to as “word lines”) and columns (often referred to as “digit lines”), where the number of rows and columns is usually a power of two. Sometimes, the array is “square” and the number of rows equals the number of columns.
In general, a DRAM array comprises a multiplicity of capacitors to store data. The capacitors are known as cells and each store a single bit of data, either a logic high (1) or a logic low (0). Specifying a particular row and column will address a single memory cell. In the case of a 1024×1024 array (or a 2 to the 10
th
power×2 to the 10
th
power array) a single memory cell would have a 10-bit row address and a 10-bit column address.
All capacitors in the array have an uncommon and common node. The common node is known as a cell plate and has a voltage that is Vcc/2, where Vcc is the voltage supplied to the chip. To store a logic high (1) in a cell, the uncommon node is charged to Vcc through an associated access transistor. To store a logic low (0), the uncommon node (storage node plate) is discharged to ground through the access transistor. A word line (row) signal line is tied to the gate of the access transistor to control access transistor operation.
The data of a cell is read by first equilibrating the cell plate and all digit lines to equilibration voltage Vcc/2. The equilibration voltage is removed and the access transistor for that cell is turned on by supplying an appropriate word line signal. This causes the charge of the capacitor to be dumped to one digit line of a digit line pair. The other digit line of the digit line pairs is used as a reference. If the storage node plate of the capacitor had been charged to Vcc, the voltage on the dumped to digit line of the digit line pairs will increase slightly. Conversely, if the storage node plate had been grounded, the voltage on the digit line will decrease slightly.
The voltage difference between the two digit lines of the digit line pairs is often on the order of 200 mV. Accordingly, the voltage difference is amplified by cross-coupled sense amplifiers (N-sense and P-sense amplifiers) by pulling the digit line with the slightly lower voltage to ground and the digit line with the slightly higher voltage to Vcc. Thereafter, the voltages of the digit line pairs are transferred out of the array to a column decoder and read by an output buffer. This read operation, however, discharges the capacitor of the cell. As such, the same or different logic values are written back to the cell for future use.
Unfortunately, as time passes, the capacitor constituting the cell gradually loses its charge and the data stored therein cannot be accurately read. To prevent data loss, all cells are refreshed periodically in a refresh operation that is similar to a read operation except the data is not actually read. For reference purposes, according to industry standard since about 1970 for a standard DRAM device, a refresh operation occurs about every 15.6 microseconds (refresh rate) for at least one row in an array. Thus, to refresh all rows in a 1024 row×1024 column array, for example, a complete refresh would take about 16 milliseconds or 15.6 microseconds times 1024 rows.
The two basic means of performing the refresh operation are distributed and burst refresh and each can be accomplished by well known RAS (row address strobe) only refresh, CAS (column address strobe) before RAS refresh, and hidden refresh techniques.
In a distributed refresh, all rows are systematically one-at-a-time refreshed by applying evenly-timed row refresh cycles. In a burst refresh, a series of refresh cycles are performed one right after another until all rows are refreshed and then a lag period exists before refresh beings again. When not being refreshed, distributed refresh allows the DRAM to be written to or read from while burst refresh prevents it. Distributed refresh is the more common refresh of the two.
Since its introduction in 1970, DRAM arrays have become more complex and densely fabricated. As such, the occurrences of electrically shorting rows-to-columns has increased. The principle causes of such shorts includes particle contamination and process variability.
In general, a row-to-column short is a point defect that, as its name implies, electrically shorts together a particular row (word line) to a perpendicular column (digit line). As expected, such shorts ruin integrity of the array. Redundant or spare rows and columns are usually fabricated within the array along with redirection circuitry to substitute functional spare rows and columns for those that are shorted—at least to the extent that shorted rows and columns do not exceed the number of spare rows and columns. Even though this redundancy exists, it is important to realize that the shorted rows and columns are not actually disconnected from the array (this is presently impractical, if not impossible due to the minuscule pitch between rows and columns). They are simply no longer addressed.
Adversely, this creates the potential for biased voltage pull down with the attendant problems of excessive standby current, read/write operations resulting in invalid data and possible damage to good cells in the array. For example, in standby power mode, all word lines (rows) are held to ground while the digit lines (columns) are held to Vcc/2 in anticipation of a new access. But, since the row is shorted to the column in at least one cell, Vcc/2 becomes shorted to ground which results in a much higher standby power mode current than is otherwise necessary or even desired.
Some prior art DRAM devices have used well known “bleeder” circuits in an attempt to combat this problem. In such a circuit, the amount of current used to hold a digit line to Vcc/2 is limited, thereby limiting power consumption during a short.
This shorting problem further exacerbates itself in DRAM devices having upper and lower or adjacent arrays that are supposed to be electrically isolated from one another. For example, the isolation devices, that serve to isolate one array from the other, trigger a logic high isolation signal during standby power mode times thereby cross-coupling one array to the other (through the sense amplifiers) and, in the event a row-to-column short exists, the standby power mode current leaks twice as much current (which increases power consumption) as it would if the arrays were in fact isolated.
With reference to
FIG. 1
, a plurality of prior art signal waveforms are shown to illustrate the problem. Word line signal waveform (WL
110
) is shown as it sequentially transitions between logic high
112
and logic low
114
values for all array rows (i, i+1, etc.) in both the upper and lower arrays. It will be appreciated that WL
110
is not a single word line signal but a plurality of word line signals, one for each cell, graphically superimposed as one signal. A break
116
in the signal waveform is shown to depict where signal waveforms transition between the upper and lower array during first and second halves of a refresh operation.
Correspondingly, the isolation signal for the upper array (ISO Upper
113
) is logic high
112
during the time interval from time
118
to before time
128
when the word line signal waveform WL
110
transitions to activity in the lower array. It is logic low
114
Dinh Son T.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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