Low power clock buffer with shared, clocked transistor

Details Low power clock buffer with shared, clocked transistor Low power clock buffer with shared, clocked transistor

1999-06-30

2000-10-03

Nguyen, Tan T.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326104, 326108, H03K 19096

Patent

active

061278505

ABSTRACT:
A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-down transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. This circuit may be found useful in clock buffering applications.

REFERENCES:
patent: 5831453 (1998-11-01), Stamoulis et al.
patent: 6049230 (2000-04-01), Durham et al.

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