Low-power address decoder

Details Low-power address decoder Low-power address decoder

1982-09-29

1984-12-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, 307449, G11C 1300

Patent

active

044882661

ABSTRACT:
A low-power address decode logic circuit capable of and a method for decoding input address signals and for providing appropriate output address driver signals for retrieving selectively contents stored in memory. A first chargeable device connected to a first node is charged to provide that node with a logic high voltage level during the first of three successive time intervals, is allowed to remain charged or is discharged to provide a logic low voltage level on the first node in accordance with the decoded output of an input NOR gate which decodes the input address signals, while simultaneously gating to an output bootstrap driver a portion of the charge stored on the first chargeable device to cause a desired logic state voltage level to be stored in the driver during the second time interval, and using this logic state voltage level stored in the driver to bootstrap control the output address driver signal during the third time interval. The circuit and method are particularly adaptable for use in decoding input address signals shard between two or more memories, typically a ROM and a RAM.

REFERENCES:
patent: 3665473 (1972-05-01), Heimbigner
patent: 3806880 (1974-04-01), Spence

Affiliated with

Also associated with

Rating

Low-power address decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-power address decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-power address decoder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1467814