Low overhead memory designs for IC terminals

Details Low overhead memory designs for IC terminals Low overhead memory designs for IC terminals

1997-09-19

1999-03-16

Santamauro, John

Electronic digital logic circuitry

With test facilitating feature

326 40, 371 2232, H03K 1900, G01R 3128

Patent

active

058835245

ABSTRACT:
An integrated circuit includes a terminal which is accessible externally of the integrated circuit, and circuitry (LOB) coupled to said terminal and operable to latch at said terminal a signal applied to said terminal by a source (ICT) external to said integrated circuit.

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patent: 5317205 (1994-05-01), Sato
patent: 5420874 (1995-05-01), Kromer
patent: 5526310 (1996-06-01), Dondale
David George, "Use a Reprogrammable Approach to Boundary Scan for EPGAs", EDN Electrical Design News.
Vol. 38, No. 16, 5 Aug. 1993, pp. 97-100.

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