Low mask count self-aligned silicided CMOS transistors with a hi

Details Low mask count self-aligned silicided CMOS transistors with a hi Low mask count self-aligned silicided CMOS transistors with a hi

1998-03-13

1999-04-27

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438229, 438232, H01L 218238

Patent

active

058973486

ABSTRACT:
A method to fabricate simultaneously a CMOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The NMOS transistor and PMOS transistor in the portion of the CMOS transistor have both anti-punchthrough and salicide structures and individually with n-LDD and p-LDD structure, respectively. The structure of ESD protective devices is fabricated with self-aligned silicide but without LDD, thus the degradation of ESD protection can be solved. The problems of accumulative aberration in scaled devices can also be alleviated through using blanket ion implantation technology and salicide process to reduce the mask count as shown in the invention.

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Ajith Amerasekera et al., Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Perforance of a 0.25 .mu.m CMOS Process, 1996 IEEE, pp. 893-896, no month of publication.
K. Fujii et al., A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM, 1996 IEEE, pp. 451-454, no month of publication.

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