Low mask count CMOS process with inverse-T gate LDD structure

Details Low mask count CMOS process with inverse-T gate LDD structure Low mask count CMOS process with inverse-T gate LDD structure

1997-04-04

1998-12-29

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438227, 438228, 438230, 438225, H01L 218238

Patent

active

058541012

ABSTRACT:
A CMOS process with inverse-T gate LDD structure uses liquid phase deposition (LPD) processes to achieve a low thermal budget with only six photoresist-masks in a CMOS device. A first photoresist-mask is used to form field oxide regions. A second photoresist-mask is used to implant a P-well. Before the second photoresist-mask is removed, a first LPD oxide layer is used to cover the N-well. The second photoresist-mask is removed, and the first LPD oxide layer is used as a mask for implanting the N-well. The first LPD oxide layer is removed and a polysilicon layer is deposited on the substrate. A third photoresist-mask is used to etch the polysilicon layer to form gate-structures for the NMOS and PMOS devices. A conformal amorphous Si layer is formed on the gate-structures, followed by forming a fourth photoresist-mask over the N-well. A conformal LPD oxide layer is formed on the conformal polysilicon layer over the P-well. N-LDD regions are then implanted. An anisotropic etch is performed to form spacers on the sidewalls of the P-well gate-structure. N.sup.+ S/D regions are then implanted. Then, before the fourth photoresist-mask is removed, another LPD oxide layer is formed over the P-well to serve as a P-well mask. Spacers, P-LDD, P.sup.+ S/D regions, and an inverse-T gate are then similarly formed for the PMOS device. The N-well is covered with another LPD oxide layer, which is then covered with a BPSG layer. Fifth and sixth photoresist-masks are then formed to create contacts from the conductive layer.

REFERENCES:
patent: 5731214 (1998-03-01), Kurihara
patent: 5747368 (1998-05-01), Yang et al.
patent: 5773335 (1998-06-01), Chao

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