Low-latency two's complement bit-serial multiplier

Details Low-latency two's complement bit-serial multiplier Low-latency two's complement bit-serial multiplier

1987-12-14

1989-08-22

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 744

Patent

active

048602400

ABSTRACT:
A double precision, low-latency two's complement bit-serial multiplier operates on the fact that after both inputs have been fully read into the multiplier, the calculation has proceeded to such a stage that it may be completed with a single counter. The multiplier comprises a plurality of bit slices and an endcell connected in series. The serial bit streams of the operands are sampled by latches in each of the bit slices, and the sampled bit values are accumulated using (5,3) counters to generate partial sum output signals. The partial sum output signal for the last bit slice is the least significant word of the double precision product. The endcell comprises another (5,3) counter which accumulates propagated sum and carry output signals of the bit slices and generates the most significant word of the double precision product.

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