Low-latency architectures for high-throughput Viterbi decoders

Details Low-latency architectures for high-throughput Viterbi decoders Low-latency architectures for high-throughput Viterbi decoders

2007-12-11

2007-12-11

Lamarre, Guy (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S794000, C375S341000, C375S262000, C702S009000, C369S059220

Reexamination Certificate

active

10922205

ABSTRACT:
Digital circuits and methods for designing digital circuits are presented. More particularly, the present invention relates to error correction circuits and methods in communications and other systems. In the present invention, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoder circuits. The main idea of the present invention involves combining K-trellis steps as a pipeline structure and then combining the resulting look-ahead branch metrics as a tree structure in a layered manner to decrease the ACS precomputation latency of look-ahead Viterbi decoder circuits. The proposed method guarantees parallel paths between any two trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers. It leads to regular and simple architecture for the Viterbi decoding algorithm. The look-ahead ACS computation latency of the proposed method increases logarithmically with respect to the look-ahead step (M) divided by the encoder constraint length (K) as opposed to linearly as in prior work. The main advantage of this invention is that it has the least latency among all known look-ahead Viterbi decoder circuits for a given level of parallelism.

REFERENCES:
patent: 5042036 (1991-08-01), Fettweis
patent: 5530707 (1996-06-01), Lin
patent: 5935270 (1999-08-01), Lin
patent: 6343105 (2002-01-01), Saegusa
patent: 6539367 (2003-03-01), Blanksby et al.
patent: 2004/0243908 (2004-12-01), Box et al.

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