Low-K spacer structure for flash memory

Details Low-K spacer structure for flash memory Low-K spacer structure for flash memory

2007-11-21

2010-12-07

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000, C257SE21209

Reexamination Certificate

active

07846794

ABSTRACT:
flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

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