Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1999-10-22
2002-05-21
Sherry, Michael J. (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S584000, C438S622000, C438S623000, C438S689000, C438S692000, C438S758000, C438S761000, C438S789000, C438S790000, C257S701000
Reexamination Certificate
active
06391795
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to the formation of a composite low k dielectric layer over and between metal lines of an integrated circuit structure.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, horizontal capacitance has increased between such conductive elements. This increase in capacitance, together with the vertical capacitance which exists between metal lines on different layers, results in loss of speed and increased cross-talk. As a result, reduction of such capacitance, particularly horizontal capacitance, has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The Trikon process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture. The article goes on to state that beyond methyl silane, studies show a possible k of 2.75 using dimethyl silane in the Trikon process. The Peters article further states that in high density plasma CVD (HDP-CVD), dielectric material formed from methyl silane or dimethyl silane and O
2
can provide a k as low as 2.75; and that trimethyl silane, available from Dow-Corning, can be used to deposit low-k (2.6) dielectric films.
The use of this type of low k material has been found to result in the formation of void-free filling of the high aspect ratio space between parallel closely spaced apart metal lines with dielectric material having a lower dielectric constant than that of convention silicon oxide, thereby resulting in a substantial lowering of the horizontal capacitance between such adjacent metal lines on the same metal wiring level.
However, the substitution of such low k dielectric materials for conventional silicon oxide insulation has not been without its own problems. Formation of the low k carbon doped dielectric material by the Trikon process is much slower than the conventional formation of undoped silicon oxide dielectric material. For example, in the time it takes to form a layer of low k dielectric material by the Trikon process on a single wafer, it may be possible to deposit a conventional dielectric layer of the same thickness on as many as 5 wafers.
However, even more importantly, it has been found that the subsequent formation of vias, or contact openings, through such low k dielectric material to the underlying conductive portions such as metal lines, or contacts on an active device, can contribute to a phenomena known as via poisoning wherein filler material subsequently deposited in the via, such as a titanium nitride liner and tungsten filler material, fails to adhere to the via surfaces. Apparently the presence of carbon in the low k dielectric material formed by the Trikon process renders the material more susceptible to damage during subsequent processing of the structure. For example, contact openings or vias are usually etched in the dielectric layer through a resist mask. When the resist mask is subsequently removed by an ashing process, damage can occur to the newly formed via surfaces of the low k material resulting in such via poisoning.
As mentioned above in the Peters article, high density plasma (HDP) has also been used to form void-free low k dielectric material. In this process, a high density plasma is used with methyl silane or dimethyl silane and O
2
to form a low k silicon oxide dielectric layer having a dielectric constant said to be as low as 2.75. However, the deposition rate of HDP low k dielectric material is similar to that of the Trikon process, making it also not economically attractive for the formation of a layer of low k dielectric material.
It has also been proposed to deposit low k silicon oxide dielectric material by other processes such as by plasma enhanced chemical vapor deposition (PECVD), using CH
4
and/or C
4
F
8
and/or silicon tetrafluoride (SiF
4
) with a mixture of silane, O
2
, and argon gases. Plasma enhanced chemical vapor deposition is described more fully by Wolf and Tauber in “Silicon Processing for the VSLI Era”, Volume 1-Process Technology (1986), at pages 171-174.
While the formation of a low k silicon oxide dielectric material by PECVD is much faster than the formation of the same thickness low k silicon oxide dielectric layer by the Trikon or HDP-CVD processes (i.e., at rates approaching the deposition rate of conventional silicon oxide), low k silicon oxide dielectric material deposited by PECVD has poor filling characteristics in high aspect ratio regions, resulting in the formation of voids in the dielectric materials deposited by PECVD in the spaces between the closely spaced apart metal lines in such structures.
In one embodiment in the aforementioned Ser. No. 09/426,061, low k silicon oxide dielectric material having a high carbon doping level is formed in the high aspect regions between closely spaced apart metal lines and then a second layer comprising a low k silicon oxide dielectric material having a lower carbon content is then deposited over the first layer and the metal lines. However, since both layers are formed by the Trikon process, the deposition rate does not radically change.
In the aforementioned Ser. No. 09/425,552, a layer of silicon oxynitride (SiON) is formed over the top surface of the metal lines to serve as an anti-reflective coating (ARC), a hard mask for the formation of the metal lines, and a buffer layer for chemical mechanical polishing (CMP). Low k silicon oxide dielectric material having a high carbon doping level is then formed in the high aspect regions between closely spaced apart metal lines up to the level of the silicon oxynitride. CMP is then applied to planarize the upper surface of the low k carbon-doped silicon oxide dielectric layer, using the SiON layer as an etch stop, i.e., to bring the level of the void-free low k silicon oxide dielectric layer even with the top of the SiON layer. A conventional (non-low k) layer of silicon oxide dielectric material is then deposited by plasma enhanced chemical vapor deposition (PECVD) over the low k layer and the SiON layer. A via is then cut through the second dielectric layer and the SiON to the top of the metal line. Since the via never contacts the low k layer between the metal lines, via poisoning due to exposure of the low k layer by the via does not occur.
It would, however, be highly desirable to provide a structure having a low k dielectric layer, and process for making same, wherein a composite layer of low k dielectric material can be formed having void-free filling characteristics for high aspect ratio regions between closely spaced apart metal lines while mitigating the poisoning of vias subsequently formed in the low k dielectric material and with less reduction of throughput in the deposition apparatus, using a process wherein all steps used to form such a composite layer could be carried out in the same vacuum processing apparatus. That is, the deposition steps could be
Catabay Wilbur G.
Schinella Richard
Kilday Lisa
LSI Logic Corporation
Sherry Michael J.
Taylor John P.
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