Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2006-07-11
2006-07-11
Lam, David (Department: 2827)
Static information storage and retrieval
Read/write circuit
Precharge
C365S189090, C365S190000
Reexamination Certificate
active
07075840
ABSTRACT:
A memory system using low impedance memory bitlines that eliminate the need for a precharge clock signal. An equilibration circuit controlled by a reference voltage is connected to the first and second bitlines of a memory cell and is operable to maintain a predetermined equilibrium condition between the first and second bit lines. The equilibration circuit is operable to generate an impedance load in the first and second bit lines at a level that allows generation of differential signals in the bit lines. The memory cell bitlines can move from a sensed state “low” to the opposite state “high” without an intervening precharge, thereby providing a significant increase in performance.
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Hamilton Gary W.
Hamilton & Terrile LLP
Lam David
Sun Microsystems Inc.
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