Low energy passivation of conductive material in damascene...

Details Low energy passivation of conductive material in damascene... Low energy passivation of conductive material in damascene...

1999-06-09

2001-01-09

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S645000, C438S650000, C438S678000, C438S701000, C438S740000

Reexamination Certificate

active

06171949

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to a manufacturing method for dual damascene semiconductors.
BACKGROUND ART
In the process of manufacturing integrated circuits, after the individual devices such as the transistors have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization” and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique, starts with the placement of a first channel dielectric layer, which is a silicon dioxide or other oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of the first channels. An anisotropic etch, generally an oxide etch, is then used to etch out the channel dielectric layer to form the first channel openings. The damascene step photoresist is then stripped and a conductive material is deposited in the first channel openings.
Some conductive materials, such as copper, require preparatory steps before deposition. An optional adhesion material, such as tantalum or titanium, is deposited followed by a barrier material, such as tantalum nitride or titanium nitride. The combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein. The barrier layer is used to prevent failure causing diffusion of the conductive material of the channels into the dielectric layer and the semiconductor devices. A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent electro-deposition of the conductive material.
The conductive material deposited in the first channel openings is then subjected to a chemical-mechanical polishing process which removes the materials above the first channel dielectric layer and above the first channel openings. With the chemical-mechanical polishing, the conductive material is “damascened” into the first channel dielectric layer to form the first conductive channels. After the chemical-mechanical polishing process the conductive material in the channels is passivated by deposition of a thin dielectric layer. The thin dielectric layer protects the conductive material from oxidation and prevents the diffusion of the conductive material into subsequent dielectric layers.
For multiple layers of channels, the “dual damascene” technique is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin dielectric etch stop layer, such as a silicon nitride, over the first channels and the first channel dielectric layer. Subsequently, a via dielectric layer is deposited on the etch stop layer. This is followed by deposition of a thin via dielectric etch stop layer, generally another nitride layer. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A stop layer etch, generally a nitride etch, is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer is then deposited over the via dielectric stop layer and the exposed via dielectric layer. A second damascene step photoresist is placed over the second channel dielectric layer and is photolithographically processed to form the pattern of the second channels. An anisotropic etch is then used to etch the second channel dielectric layer and the via dielectric layer to form the second channel openings and the via areas down to the thin etch stop layer above the first channels. The damascene photoresist is then removed, and a stop layer etch process removes the via etch stop layer above the first channels in the via areas.
For conductive materials such as copper as previously described, a barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to simultaneously fill the second channel and the vias. A second chemical-mechanical polishing process defines the second channel and leaves the two vertically separated channels connected by a cylindrical via. Again, after the chemical-mechanical polishing process the conductive material in the channels is passivated by deposition of a dielectric layer. The dielectric layer protects the conductive material from oxidation and prevents the diffusion of the conductive material into subsequent dielectric layers.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
For conductive materials, such as copper, the protective dielectric layer is generally of silicon nitride. Unfortunately, with smaller and smaller semiconductor geometries, since the dielectric constant of silicon nitride is relatively high, it causes capacitance problems between the channels and between the interconnect layers.
DISCLOSURE OF THE INVENTION
The present invention provides a method for dry passivation of the surface of exposed conductive materials in semiconductor integrated circuits to protect from oxidation and prevent diffusion. After deposition of a conductive material, such as copper, and chemical-mechanical polishing, a low energy implantation process is used to nitride the conductive material.
The present invention provides a method for passivating the surface of exposed conductive materials in semiconductor integrated circuits without using a high dielectric constant protective layer such as SiN.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5314833 (1994-05-01), Lee et al.
patent: 5371047 (1994-12-01), Greco et al.
patent: 5707895 (1998-01-01), Wuu et al.
patent: 5861328 (1999-01-01), Tehrani et al.

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