Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-23
2003-04-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06553529
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly a timing system and associated methods for use in a semiconductor device tester.
BACKGROUND OF THE INVENTION
Automatic test equipment serves a key manufacturing role in the fabrication of semiconductor devices. Commonly individually referred to as a “tester”, the individual units verify the operability of each device at both the wafer (via probe testing) and packaged-device levels.
Commercially successful tester designs typically provide a semiconductor manufacturer with a combination of features specific to one or more particular applications. Desirable features usually involve a combination or trade-off of criteria such as cost, flexibility, accuracy, and ease of use. Generally speaking, the more features included in a tester, the higher the cost.
One of the critical tester sub-systems especially sensitive to the criteria noted above is the timing generation circuitry. A tester timing system generally establishes precise signal delays during a device-under-test (DUT) test cycle according to pre-programmed pattern data. The delays serve to mark the specific test events for the tester driver/comparator circuitry (such as drive to high, drive to low, strobe, etc.)
Conventional high-resolution timing systems utilize timing generators that employ coarse, medium and fine delay circuitry to produce timing resolutions (minimally selectable timing increments) on the order of picoseconds. The coarse delay circuitry includes, for example, a synchronous counter that produces an output based on integer multiples of the input clock.
To achieve medium and fine delays in conventional timing generators, interpolators are typically used. The medium delay is often realized by a plurality of delay elements that split the system clock signal into “medium” sliced time intervals. The fine delay is generally achieved by a delay circuit that usually includes a pair of analog inputs, one to receive a ramping voltage signal, and the other to receive the output from a digital-to-analog converter (DAC). The DAC converts a digital word representing a desired delay into a threshold voltage. When the ramping voltage reaches the threshold set by the DAC, the interpolator generates a signal offset by a fine fractional portion of the system clock.
One of the more desirable features of the analog interpolator involves the optional ability to change the delay value from the DAC “on-the-fly”, from period to period. A highly flexible tester that employs interpolators having such “on the fly” capabilities for both period switching and timing switching is the model J973 tester manufactured by Teradyne, Inc., of Agoura Hills, Calif. This tester additionally includes an edgeset memory for storing pre-programmed timing values to control the timings for the various interpolators. While the circuitry and software required to effect on-the-fly changes generally substantially increases the cost of a tester, the capability provides a high level of flexibility in testing DUT's operating up to 250 MHz.
In an effort to minimize the cost associated with testing DUT's, while maintaining an acceptable level of flexibility, one proposal for a timing system employed “fixed” interpolators with no edgeset memory to provide a somewhat limited pallette of timing selections during DUT periods. The proposal, included in the Teradyne Model J921 Tester, manufactured by Teradyne Inc. of Agoura Hills, Calif., pre-set the interpolators such that the analog delay values could not change on the fly. The delay values were set according to user specifications to offer a selection of timing delays corresponding to the number of timing generators in the system. The system thus minimized costs by omitting the “on-the-fly” circuitry, and edgeset memory while offering a somewhat reduced level of timing flexibility.
While beneficial for its intended applications, the conventional fixed interpolator approach described above lacked the level of flexibility desired by some semiconductor manufacturers. The inflexibility resulted from the perceived lack of timing choices from the single set of fixed interpolators. While the selection could be increased by providing more interpolators, the additional hardware would offset any advantages inherent in omitting the “on-the-fly” circuitry.
More recently, as the operating speeds of semiconductor devices reach and surpass the gigahertz range, the desirability of costly “on-the-fly” circuitry and software has diminished. The reason involves the relatively few types of waveforms utilized at such speeds. With few waveforms to emulate, tester timing flexibility is not as critical.
Although tester timing flexibility isn't as critical for high-speed DUT's, many high speed semiconductor devices also implement relatively “slow-speed” ports (around 100 to 200 MHz). Thus, in order to completely test such devices, both high speed and slow speed patterns are required. Consequently, without the perceived testing advantages associated with highly flexible timing systems, many manufacturers are hesitant to invest in testers that omit the feature. The result is that manufacturers often purchase costly testers that provide more functionality than is actually required for a majority of the testing.
What is needed and heretofore unavailable is a fixed interpolator timing system that provides high speed, high resolution and low flexibility test capability with high accuracy. Moreover, such a system is needed that also provides low-speed, moderate resolution and high flexibility test capability at fairly high accuracies. Additionally, the need exists for such a system to be relatively low cost. The timing system and method of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The timing system of the present invention provides multi-modal semiconductor device test capabilities including a high-speed high accuracy mode and a low-speed high flexibility mode to test DUT pins requiring varying signal rates. Moreover, the timing system construction provides a straightforward user interface and low cost hardware architecture.
To realize the foregoing advantages, the invention in one form comprises a timing system that responds to pattern generation circuitry for producing test patterns for application to a device-under-test. The timing system includes a timing memory circuit that stores programmed edge timings for the patterns. The timing system further includes timing logic having a master oscillator and a plurality of fixed edge generators. The fixed edge generators are responsive to the programmed edge timings to produce the event timing signals.
In another form, the invention comprises a semiconductor tester for testing a device-under-test having a combination of high-speed and low-speed pins. The tester includes a test controller having a pattern memory and a user interface and a pattern generation circuit having respective high-speed and low-speed modes for selectively producing test patterns according to the pattern memory for application to the device-under-test according to a DUT clock period. A system bus connects to the test controller and the pattern generation circuit for routing command and data signals therebetween. The tester further includes drive/compare circuitry adapted for coupling to the device-under-test and a failure processing circuit disposed between the system bus and the drive/compare circuitry. A timing system generates event timing signals corresponding to predefined user settings. The timing system includes a timing memory circuit that stores programmed edge timings for the patterns. The timing system further includes timing logic including a master oscillator and a plurality of fixed edge generators. The fixed edge generators are configured to provide a fixed selection of timing signals corresponding to the fixed number of edge generators within a predetermined clock period.
In yet another form, the invention comprises a method of g
De'cady Albert
Dooley Matthew C.
Kreisman Lance M.
Teradyne, Inc.
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