Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
1998-06-24
2001-06-19
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S697000
Reexamination Certificate
active
06248651
ABSTRACT:
The present invention relates to an improved method of fabricating transient voltage suppressor semiconductor devices or the like, which involves abrading the substrate surface before diffusion to a degree short of polishing, followed by diffusion which results in devices functionally the equal to of those more costly devices produced by the conventional polishing operation.
BACKGROUND OF THE INVENTION
Transient voltage suppressor devices are essentially diodes designed to be incorporated into an electrical circuit to protect that circuit against excessive voltage by breaking down and conducting if the voltage applied to them exceeds a predetermined value. Such devices usually constitute two such diodes electrically connected in opposing relation so as to protect against excessive voltage in either direction. The breakdown voltage at which such devices function depends to a large extent on the impurity concentration and depth of diffusion into the substrate. Hence variations in those parameters and particularly depth of diffusion at different points across the surface of the substrate are most undesirable. For that reason it has in the past been thought to be essential, if an effective yield of properly acting devices is to be obtained, that the substrate surfaces must be highly polished, and anything short of that high polish was thought to be commercially excluded. Polishing is an extremely time-consuming process, and when it is considered that bi-directional transient voltage suppressors of the prior art require that both opposing surfaces of the substrate be polished, the economic problems presented by the need for polishing are doubled.
Industry standard steps for obtaining a prior art mirror-like polished surface on a substrate include saw slicing, mechanical lapping, cleaning, edge rounding, caustic etch, another cleaning, followed by a multi-step, chemical and mechanical, polishing, followed by a final cleaning step. The polished surfaces thus produced are very prone to damage by handling or otherwise.
SUMMARY OF THE INVENTION
In accordance with the present invention, in order to produce the desired optimum mirror-like surface on the wafer, but in a fraction of the time previously required for polishing, a non-polishing grinding process is employed of the type disclosed in U.S. Pat. No. 5,360,509 of Nov. 1, 1994 entitled “Low Cost Method of Fabricating Epitaxial Semiconductor Devices” and owned by the assignee of this application. As a result, and as set forth in that patent, while with mechanically polished devices polishing on one side alone alone has taken 1 to 2 hours, by way of contrast the grinding in the present process takes but 2 to 4 minutes per side. The grinding may be followed in the present process by an optional etching step, but that etching step takes only about 2 minutes. Hence the time comparison of the present process as compared to the polishing process for a bi-directional device involves a comparison of at most 10 minutes to 4 hours. The consequent saving in cost of production is obvious.
In the aforementioned U.S. Pat. No. 5,360,509, the grinding process is followed by epitaxial introduction of impurities. That process of impurity introduction is itself relatively costly. Other less costly impurity introduction methods are known, among which is the use of a solid impurity source from which the impurity is diffused into the substrate. However, because of the tightness of the breakdown voltage requirement for devices of the type under discussion and the sensitivity of the breakdown voltage at a given point on the surface of the substrate to the precise depth of the P-N junction at that point, with that depth being a function of the smoothness of the surface into which the impurities is diffused, it had been thought in the past that in order to use solid source diffusion for devices of this type the substrate surfaces exposed to the impurities must be exceedingly highly polished.
We have discovered that by using the non-polishing grinding procedure here described solid source diffusion can be used to produce accurate devices, especially of the bi-directional type, with high production yield and at a very significantly reduced cost.
By way of example, the cost of a cut wafer suitable for products of the type under discussion is about $8 for a 4″ wafer. If that wafer is subjected to normal polishing on one side its cost is about $15 and if it is subjected to polishing on both sides its cost is about $30. The roughness of the cut surface, measured from peak-to-valley, is in excess of 5,000 Angstroms, whereas the peak-to-valley roughness of a polished surface is about 20 Angstroms. By way of contrast the peak-to-valley surface roughness produced by the grinding process here described is about 150 Angstroms. The cost of the wafers ground on only one side is about $10 and the cost of that wafer ground on both sides is about $12. The comparison is therefore between $30 and $12 for a 4″ wafer ground on both sides, quite a significant saving in wafer costs without any sacrifice in breakdown voltage precision.
It is the prime object of the present invention, therefore, to devise a process for the formation of transient voltage suppressor semiconductors on a substrate which will be less time-consuming and costly than prior art methods but which will produce voltage suppressor devices of at least equal functional quality as compared to devices made by the prior art polishing process.
REFERENCES:
patent: 3436259 (1969-04-01), Regh et al.
patent: 4711256 (1987-12-01), Kaiser
patent: 4935386 (1990-06-01), Nakagawa et al.
patent: 5104828 (1992-04-01), Morimoto et al.
patent: 5137597 (1992-08-01), Curry, II et al.
patent: 5190064 (1993-03-01), Aigo
patent: 5201958 (1993-04-01), Breunsbach et al.
patent: 5223080 (1993-06-01), Ohta et al.
patent: 5227339 (1993-07-01), Kishii
patent: 5240883 (1993-08-01), Abe et al.
patent: 5360509 (1994-11-01), Zakaluk et al.
Japanese Abstracts JP 61166133 and JP 59035421 Silicon Processing for the VLSI Era. pp. 23-25 Lattice Press 1986.
VLSI Technology, pp. 34-39 McGraw, Hill (1983).
Integrated Circuits, p. 274, Motorola, 1965.
Semiconductor Silicon Crystal Technology, 1987, Academic Press, 1989.
A Future Technology for Silicon Wafer Processing for USLI, pp. 251-255 (1991).
Backgrinding Wafters For Maximum Die Strength Sharon Lewis, Micron Technology Inc., Jul. 1992 pp-86-89.
Internal gettering heat treatments and oxygen precipitation in Epitaxial silicon wafers—W. Wijaranakula, P.M. Burke and L. Forbes, 1986 Materials Research Society pp-693-697.
Epi's Leading Edge, Semiconductor International Jun. 1991 pp.68-71.
Substrate Surface Preparation and Its Effect on Epitaxial Silicon, P. Rai-Choudhury, pp. 1183-1189, 1971.
A Chemical Polish Method For The Preparation Of Silicon Substrates For Epitaxial Deposition Fairhurst and Rich, pp. 15-18 (1966).
Mechanical Thinning Of InP Wafer by Grinding, Nishiguchi et al., pp. 1826-1831 (1991).
U.K. Patent No. 1,126,639 Flat Grinding of Semiconductor Wafers—Report of Dr. Hubert Hinzen.
Amato John
Chan Joseph
Eng Jack
Garbis Dennis
Zakaluk Gregory
Epstein Robert L.
General Semiconductor Inc.
James Harold
James & Franklin LLP
Mulpuri Savitri
LandOfFree
Low cost method of fabricating transient voltage suppressor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low cost method of fabricating transient voltage suppressor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low cost method of fabricating transient voltage suppressor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2462778