Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step
Patent
1993-03-08
1994-11-01
Thomas, Tom
Adhesive bonding and miscellaneous chemical manufacture
Delaminating processes adapted for specified product
Delaminating in preparation for post processing recycling step
156626, 156643, 437225, H01L 21306
Patent
active
053605098
ABSTRACT:
Significant reductions in the cost of fabrication of epitaxial semiconductor devices without sacrifice of functional characteristics is achieved by eliminating the conventional but costly polishing procedure, instead subjecting the substrate to grinding, cleaning and etching processes in which the grinding removes material from the surface to a depth of at least 65 microns and the etching further removes material to a depth of about 6-10 microns, the grinding preferably being carried out in two steps, the first being a coarse step and the second being a fine step, with the rotated grinding elements dwelling at their respective last grinding positions for a short period of time. The result is the equivalent of the prior art polishing procedure which took considerably longer to carry out and which therefore was much more costly. Complementing this grinding procedure is an improved and cost effective epitaxial process utilizing a unique two-step hydrochloric gas high temperature etch and a faster growth rate process with shorter cycle steps. In addition, oxygen control and "gettering" capabilities result in a total process improving the economics of formation of epitaxial semiconductor devices.
REFERENCES:
patent: 4711256 (1987-12-01), Kaiser
patent: 5104828 (1992-04-01), Morimoto et al.
patent: 5137597 (1992-08-01), Curry, II et al.
patent: 5190064 (1993-03-01), Aigo
patent: 5201958 (1993-04-01), Breunsbach et al.
patent: 5223080 (1993-06-01), Ohta et al.
patent: 5227339 (1993-07-01), Kishii
patent: 5240883 (1993-08-01), Abe et al.
"Flat Grinding of Semiconductor Wafers"--Hinzen; Semiconductors IDR 3, 1992.
"A future technology for silicon wafer processing for ULSI"--Abe; Precision Engineering Oct. 1991, pp. 251-255.
"Background Wafers for Maximum Die Strength"--Lewis; Semiconductor International, Jul. 1992, pp. 86-89.
"Internal gettering heat treatments and oxygen precipitation in epitaxial silicon wafers"--Wijaranakula, Burke and Forbes; Journal of Materials Research, vol. 1, No. 5, Sep./Oct. 1986, pp. 693-697.
"Epi's Leading Edge"--Burggraaf; Semiconductor International, Jun. 1991, pp. 68-71.
"Mirror Surface Grinding of Silicon Wafer with Electrolytic in Process Dressing"--Ohmori and Nakatawa.
Chan Joseph Y.
Garbis Dennis
Laterza Lawrence
Latza John
Zakaluk Gregory
GI Corporation
Picardat Kevin M.
Thomas Tom
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