Low-cost high-performance planar back-gate CMOS

Details Low-cost high-performance planar back-gate CMOS Low-cost high-performance planar back-gate CMOS

2005-08-08

2008-01-01

Toledo, Fernando L. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S045000, C438S369000, C438S524000, C438S914000

Reexamination Certificate

active

07314794

ABSTRACT:
A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.

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