Low-cost configuration for monitoring and controlling...

Details Low-cost configuration for monitoring and controlling... Low-cost configuration for monitoring and controlling...

1999-02-05

2002-04-16

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S763010

Reexamination Certificate

active

06374379

ABSTRACT:

This invention relates generally to automatic test equipment, and more specifically to the use of programmable digital devices for monitoring and controlling parametric measurement units in automatic test equipment.
Automatic test equipment (also known as a “tester”) is widely used to test semiconductor devices, printed circuit boards, and other electronic components and assemblies. Many testers, especially those that are used to test semiconductor devices, use “pin slice” architecture. Such testers generally include multiple pin slice circuits, each associated with a separate pin on a device under test (DUT). Further, each pin slice circuit generally includes circuitry for generating and measuring signals at its associated pin on the DUT.
A typical tester may generate and measure signals on hundreds to a few thousand pins, each pin having its own pin slice circuitry. This means that pin slice circuitry is duplicated hundreds or thousands of times in a tester. It is therefore very important for testers to use pin slice circuits that are both area and cost efficient.
In addition, during a typical test session, it is often necessary to vary one or several analog reference voltage levels used in each pin slice circuit. This is especially the case when performing parametric tests of a DUT's drive and receive levels.
For example, a sequence of reference voltage levels may be generated and provided to certain sections of the pin slice circuits. If the steps of generating and providing changes in the reference voltage levels require a large amount of time, then the time to complete the full test session could become very long, especially if the test session calls for the generation of sequences of hundreds of different reference voltage levels. It is therefore very important for testers to communicate the desired reference voltage level changes and generate new reference voltage levels quickly.
However, pin slice circuits must also generate and measure signals with a high degree of accuracy. This is because any inaccuracy in signal levels generated or measured by pin slice circuits will generally affect the accuracy of test results. In particular, it is very important for pin slice circuits to generate stable voltage and current levels during parametric tests. Further, pin slice circuits must generate and measure signals at levels that are compatible with the semiconductor devices being tested.
One way of satisfying these competing requirements is to design pin slice circuits using a combination of different component technologies. For example, pin slice circuits have been designed using a combination of CMOS and bipolar component technologies.
Primarily because of the low power requirements of CMOS components, CMOS has become the technology of choice for many designers of computers and electronic devices. Consequently, CMOS components have become widely available and relatively inexpensive. Further, because of the desire to make computers and electronic devices both faster and smaller, the dimensions of CMOS components have decreased significantly over the years. Accordingly, portions of pin slice circuits have been designed using CMOS technology in an effort to make the circuits lower cost and more compact.
However, one shortcoming of designing circuits using CMOS technology is that it can lead to unstable and unpredictable timing characteristics. For example, timing characteristics of identical CMOS circuits have been found to vary from component-to-component.
Further, timing characteristics of CMOS components have been found to vary with temperature. For example, as frequencies of signals processed by CMOS components increase, power requirements of the CMOS components also generally increase, thereby causing the components to heat-up. This increase in temperature can affect propagation delays through the CMOS components.
Generally, this shortcoming of CMOS technology does not seriously affect the performance of most computers and electronic devices because CMOS circuits in these devices are usually synchronized with an internal clock. Such synchronous design techniques are often used to enhance the stability and predictability of electronic circuits.
Although some portions of pin slice circuits can also be synchronized with a clock inside the tester, the timing of other portions of pin slice circuits cannot be similarly synchronized. For example, the times at which pin slice circuits generate and measure signals at pins of a DUT are usually determined by the DUT, not by a clock internal to the tester.
Accordingly, when CMOS technology is used to implement circuitry for generating timing signals in pin slice circuits, compensation techniques must generally be used to improve the timing characteristics of the CMOS circuitry. Such compensation techniques are described in U.S. patent application Ser. No. 08/510,079, assigned to TERADYNE®, Inc., Boston, Mass., USA.
Another reason why CMOS technology is sometimes not used to implement the signal generation portions of pin slice circuits is that CMOS circuits generally have low drive capabilities.
For these reasons, bipolar technology is often used for implementing signal generation and measurement portions of pin slice circuits in conventional testers. Timing characteristics of circuits made with bipolar technology are generally more stable and more predictable than CMOS circuits. Further, bipolar circuits can generally drive and measure signals at higher power levels than CMOS circuits.
Such a conventional tester
100
is shown in FIG.
1
. The tester
100
includes a test system controller
110
, which includes a special purpose computer (not shown); and, a memory
124
, which stores test results and information needed to control the tester
100
. Both the test system controller
110
and the memory
124
are normally implemented using CMOS technology. This is because the test system controller
110
and the memory
124
are typically synchronized with a test system clock. Further, neither the test system controller
110
nor the memory
124
is required to drive or receive signals with high power levels.
The tester
100
also includes multiple pin slice circuits
114
, which generate and measure signals at separate pins of a DUT
112
, which might be a discrete semiconductor device or one of a plurality of dies on a semiconductor wafer.
Each pin slice circuit
114
typically has portions that are implemented using either CMOS or bipolar technology. For example, the pin slice circuits
114
include timing generators
116
, which may be implemented using CMOS technology. In this case, the compensation techniques mentioned above are typically used to improve timing characteristics of the CMOS circuits. The timing generators
116
produce timing signals in response to commands from the test system controller
110
for determining times at which driver/receiver channels
118
drive or measure digital signals at pins of the DUT
112
.
The driver/receiver channels
118
in the pin slice circuits
114
are typically implemented using bipolar technology. This ensures that the driver/receiver channels
118
have the capability of driving and measuring digital signals at pins of the DUT
112
at the proper times.
Two of the pieces of information that the test system controller
110
uses to control the pin slice circuits
114
indicate values of logical high and logical low levels to be provided by the driver/receiver channels
118
to the DUT
112
; and, values of logical high and logical low levels to be received by the driver/receiver channels
118
from a properly functioning DUT
112
.
In particular, the pin slice circuits
114
include reference voltages
122
, which are typically implemented using discrete analog circuitry. The reference voltages
122
provide multiple reference voltages to the driver/receiver channels
118
. Accordingly, the test system controller
110
provides information to the driver/receiver channels
118
indicating which reference voltages to use as logical high levels and logical low levels.
The pin slice

Affiliated with

Also associated with

Rating

Low-cost configuration for monitoring and controlling... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-cost configuration for monitoring and controlling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-cost configuration for monitoring and controlling... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2885345