Low-cost and ultra-fine integrated circuit packaging technique

Details Low-cost and ultra-fine integrated circuit packaging technique Low-cost and ultra-fine integrated circuit packaging technique

2007-04-27

2009-08-18

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S774000

Reexamination Certificate

active

07576435

ABSTRACT:
A semiconductor package structure and the methods for forming the same are provided. The semiconductor package structure includes an interposer; a first plurality of bonding pads on a side of the interposer; a semiconductor chip; and a second plurality of bonding pads on a side of the semiconductor chip. The first and the second plurality of bonding pads are bonded through metal-to-metal bonds.

REFERENCES:
patent: 5202754 (1993-04-01), Bertin et al.
patent: 5477933 (1995-12-01), Nguyen
patent: 6548391 (2003-04-01), Ramm et al.
patent: 6914786 (2005-07-01), Paulsen et al.

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