Stock material or miscellaneous articles – Web or sheet containing structurally defined element or... – Physical dimension specified
Reexamination Certificate
2000-12-29
2004-10-19
Thibodeau, Paul (Department: 1773)
Stock material or miscellaneous articles
Web or sheet containing structurally defined element or...
Physical dimension specified
C428S335000, C428S457000, C428S469000, C428S473500, C438S009000, C216S067000, C118S7230AN
Reexamination Certificate
active
06805952
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor wafers, and, more particularly, to plasma etching chambers having components that reduce particle contamination during processing.
2. Description of the Related Art
In the field of semiconductor processing, vacuum processing chambers are generally used for etching and chemical vapor depositing (CVD) of materials on substrates by supplying an etching or deposition gas to the vacuum chamber and application of an RF field to the gas to energize the gas into a plasma state. Examples of parallel plate, transformer coupled plasma (TCP™) which is also called inductively coupled plasma (ICP), and electron-cyclotron resonance (ECR) reactors and components thereof are disclosed in commonly owned U.S. Pat. Nos. 4,340,462; 4,948,458; 5,200,232 and 5,820,723.
In semiconductor integrated circuit fabrication, devices such as component transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. Metallic interconnect lines, which are typically etched from a metallization layer disposed above the wafer, may then be employed to couple the devices together to form the desired circuit. The metallization layers typically comprise copper, aluminum or one of the known aluminum alloys such as Al—Cu, Al—Si or Al—Cu—Si. An anti-reflective coating (ARC) layer and an overlying photoresist (PR) layer, may be formed on top of the metallization layer. The ARC layer typically comprises a titanium containing layer such as TiN or TiW. To form the aforementioned metallic interconnect lines, a portion of the layers of the layer stack, including the metallization layer, can be etched using a suitable photoresist technique. The areas of the metallization layer that are unprotected by the mask may then be etched away using an appropriate etching source gas, leaving behind metallization interconnect lines or features.
To achieve greater circuit density, modern integrated circuits are scaled with increasingly narrower design rules. As a result, the feature sizes, i.e., the width of the interconnect lines or the spacings (e.g., trenches) between adjacent interconnect lines, have steadily decreased. To form the narrow conductor lines of modern integrated circuits, highly anisotropic etching is desired. Etch anisotropy refers to the rate of vertical etching compared to the rate of lateral etching. In order to form high aspect ratio features with vertical sidewalls, the rate of vertical etching must be significantly greater than the rate of lateral etching. In plasma etching, vertical profiles are often achieved using sidewall passivation techniques. Such techniques typically involve introducing a polymer forming species (usually fluorocarbons such as CF
4
, CHF
3
, C
4
F
8
) into the reaction chamber during etching. The polymer which forms during etching is preferentially deposited on the sidewalls of the etched features thereby reducing lateral etching of the substrate and increasing etch anisotropy. During the etching process, however, polymer deposits can also form on the interior surfaces of various components of the etch chamber which are exposed to the plasma. Over time, these polymer deposits can flake or peel off thus becoming a source of particle contamination in the plasma reactor.
The polymer deposits formed inside the plasma reactor typically comprise chain molecules of carbon compounds. When the polymer contacts and adheres to the substrate being processed, it can contaminate that portion of the substrate and reduces the die yield therefrom. Polymer deposits can accumulate on all chamber surfaces, particularly on the surfaces of the chamber housing adjacent the process gas inlet tubes, as well as the underside of the chamber cover or gas distribution plate opposite the substrate surface. The polymer deposited on the interior surfaces of the chamber can migrate onto the substrate to create a substrate defect. Polymer particulate contamination is exacerbated by the thermal cycling of the reactor components during repeated plasma processing cycles. The repeated heating and cooling of the plasma exposed surfaces of reactor components can cause the adhered polymer deposits to exfoliate or flake off due to CTE differentials between the polymer deposits and the reactor surfaces. The polymer deposits can also become dislodged by bombardment with reactant species in the plasma.
As integrated circuit devices continue to shrink in both their physical size and their operating voltages, their associated manufacturing yields become more susceptible to particle contamination. Consequently, fabricating integrated circuit devices having smaller physical sizes requires that the level of particulate contamination be less than previously considered to be acceptable. Various methods have been employed to reduce particle contamination in plasma reactors. See, for example, U.S. Pat. Nos. 5,366,585; 5,391,275; 5,401,319; 5,474,649; 5,851,343; 5,916,454; 5,993,594; 6,120,640; and 6,155,203.
In order to reduce particle contamination, plasma reactors can be periodically cleaned to remove the polymer deposits. Plasma cleaning processes are disclosed in U.S. Pat. Nos. 5,486,235; 5,676,759; and 5,685,916. Additionally, the plasma reactor parts are typically replaced periodically with new reactor parts.
It would be desirable to provide plasma reactor components that reduce the levels of particle contamination inside the reactor chamber. The use of such parts would help to improve the yield and/or increase the period of time between cleaning or replacement of plasma reactor components.
SUMMARY OF THE INVENTION
The present inventors have discovered that particle contamination in plasma reactors can be reduced by plasma spraying a coating material such as a ceramic or high temperature polymer onto plasma exposed surfaces of the reactor. The plasma sprayed material forms a coating having desired surface roughness characteristics to promote adhesion of polymer deposits. The improved adhesion of the polymer deposits on chamber surfaces can reduce the tendency of the deposits to flake or peel off of the chamber surfaces thereby reducing the level of particulate contamination in the reactor. By improving the adhesion of polymer deposits on plasma reactor components, reactor components may need to be cleaned or replaced less frequently thereby reducing the cost of operating the plasma reactor.
According to one embodiment of the present invention, a method of making a plasma reactor component is provided. The reactor component has one or more surfaces which are exposed to plasma during use. The method includes plasma spraying a coating material onto a plasma exposed surface of the component to form a coating having surface roughness characteristics that promote the adhesion of polymer deposits.
According to another embodiment of the present invention, a component of a plasma reactor having one or more surfaces exposed to the plasma during processing is provided. The component includes a plasma sprayed coating on a plasma exposed surface thereof. The coating has surface roughness characteristics that promote the adhesion of polymer deposits.
According to another embodiment of the present invention, a plasma reactor including one or more components as set forth above and a method of processing a substrate therein are also provided. The method includes contacting an exposed surface of the substrate with a plasma.
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patent: 5486235 (
Chang Christopher C.
Steger Robert J.
Lam Research Corporation
Thibodeau Paul
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